AF3 supports VHDL code generation of component architectures(Deployment is currently not supported.). The generated VHDL codes can be simulated in the <ahref="http://www.model.com"><i>ModelSim</i></a> and
<ahref="http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm"><i>Xilinx ISE</i></a>. One of the advantages of our VHDL generator is synthesizability of the generated code. That means, the generated codes should be able to
deployed on a FPGA device.
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Because of the limitation of the synthesis only the subset of the AF3 semantic could be translated to VHDL. And the data types in AF3 are encoded as standardized data types in VHDL(SIGNED and UNSIGNED in IEEE.NUMERIC_STD package).
For example, the "division" operator is not synthesizable in most of the well known VHDL synthesis software. If you want use AF3 VHDL code generator, you should not use "/" operator in your design.
The subset of AF3 semantic, which is supported from VHDL code generator, will be listed in the table 1. Currently, the VHDL code generator supports component and component specifications for atomic component(Code specification, state automaton and mode automaton).
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@@ -37,19 +39,19 @@ A step in AF3 simulator corresponds one clock in VHDL Simulator. If the simulati
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<tdwidth="20%">Specification</td><tdwidth="10%">Yes</td><td> Code Specification, State Automaton, Mode Automaton </td>
<tdwidth="20%">Specification</td><tdwidth="5%">Yes</td><td> Code Specification, State Automaton, Mode Automaton </td>
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<tdwidth="20%">Operator</td><tdwidth="10%">Yes</td><td> +, -, *, and, or, not, >, >=, =, <, <=, != <fontcolor="red">(Notice: "/" is not supported)</font></td>
<tdwidth="20%">Operator</td><tdwidth="5%">Yes</td><td> +, -, *, and, or, not, >, >=, =, <, <=, != <fontcolor="red">(Notice: "/" is not supported)</font></td>
