Commit 125d68a1 authored by Mingjun Li's avatar Mingjun Li
Browse files

add help document for vhdl generator

refs 809
parent c1350468
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@author li
@author $Author$
@version $Rev$
@ConQAT.Rating YELLOW Hash: 23BCF5D53A495499B3372050168CA2D2
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<html>
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AF3 supports VHDL code generation of component architectures(Deployment is currently not supported.). The generated VHDL codes can be simulated in the <a href="http://www.model.com"><i>ModelSim</i></a> and
<a href="http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm"><i>Xilinx ISE</i></a>. One of the advantages of our VHDL generator is synthesizability of the generated code. That means, the generated codes should be able to
deployed on a FPGA device.
<br>
<br><br>
Because of the limitation of the synthesis only the subset of the AF3 semantic could be translated to VHDL. And the data types in AF3 are encoded as standardized data types in VHDL(SIGNED and UNSIGNED in IEEE.NUMERIC_STD package).
For example, the "division" operator is not synthesizable in most of the well known VHDL synthesis software. If you want use AF3 VHDL code generator, you should not use "/" operator in your design.
The subset of AF3 semantic, which is supported from VHDL code generator, will be listed in the table 1. Currently, the VHDL code generator supports component and component specifications for atomic component(Code specification, state automaton and mode automaton).
......@@ -37,19 +39,19 @@ A step in AF3 simulator corresponds one clock in VHDL Simulator. If the simulati
<th>Comment</th>
</tr>
<tr>
<td width="20%">Specification</td><td width="10%">Yes</td><td> Code Specification, State Automaton, Mode Automaton </td>
<td width="20%">Specification</td><td width="5%">Yes</td><td> Code Specification, State Automaton, Mode Automaton </td>
</tr>
<tr>
<td width="20%">Operator</td><td width="10%">Yes</td><td> +, -, *, and, or, not, &gt;, &gt;=, =, &lt;, &lt;=, != <font color="red">(Notice: "/" is not supported)</font> </td>
<td width="20%">Operator</td><td width="5%">Yes</td><td> +, -, *, and, or, not, &gt;, &gt;=, =, &lt;, &lt;=, != <font color="red">(Notice: "/" is not supported)</font> </td>
</tr>
<tr>
<td width="20%">Type</td><td width="10%">Yes</td><td> int(VHDL type: signed(31 downto 0)), boolean(VHDL type: boolean) </td>
<td width="20%">Type</td><td width="5%">Yes</td><td> int --&gt; signed(31 downto 0), boolean --&gt; boolean </td>
</tr>
<tr>
<td width="20%">User defined Function</td><td width="10%">No</td><td> - </td>
<td width="20%">User defined Function</td><td width="5%">No</td><td> - </td>
</tr>
<tr>
<td width="20%">User defined Enumeration</td><td width="10%">No</td><td> - </td>
<td width="20%">User defined Enumeration</td><td width="5%">No</td><td> - </td>
</tr>
</table>
<br> Table 1: The AF3 semantic supported by VHDL generator
......@@ -63,11 +65,11 @@ The VHDL generation process is very similar with C code generator. You can start
<br><br>
After that you can select a target folder, which is to be in the Eclipse workspace dictionary.
(Please use the Storage-Perspective to create Eclipse workspace projects and folders.
If you don't already have the Storage-Perspective, you can add it by pressing the
<img src="./pictures/VHDL.Select.Target.Folder.png"> button near to the Perspective buttons, select "Other..." and then select "Storage".).
If you don't already have the Storage-Perspective, you can add it by pressing the
button near to the Perspective buttons, select "Other..." and then select "Storage".).
<br><br>
<img src="./pictures/Code.Generation.Select.png">
<img src="./pictures/VHDL.Select.Target.Folder.png">
<br><br>
Once the code generation is complete, you can find the result in the Storage-Perspective. All files are stored in "VHDL-gen" folder.
......@@ -104,7 +106,7 @@ Now project is simulatable, if you have a testbench file in the project. Switch
<img src="./pictures/VHDL.ISE.simulate.view.png">
<br><br>
As result a new windows is appeared and the the simulation result should looks like in the following figure.
As result a new windows is appeared and the the simulation result should look like in the following figure.
<br><br>
<img src="./pictures/VHDL.ISE.Wave.PNG">
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@author becker
@author $Author$
@version $Rev$
@ConQAT.Rating GREEN Hash: 23155701EB0A4C4204DB7C7579455FCD
@ConQAT.Rating YELLOW Hash: 9EAB99DEA5D4536FC7EFC2BB3E71B067
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