Commit 5284a1ec authored by Mingjun Li's avatar Mingjun Li
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complement of vhdl generator document and plugin clean up for vhdl generator

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parent f010ecbb
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@author li
@author $Author$
@version $Rev$
@ConQAT.Rating YELLOW Hash: 23BCF5D53A495499B3372050168CA2D2
@ConQAT.Rating YELLOW Hash: 0CCD946787BCF8660CECA34E410F3612
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Because of the limitation of the synthesis only the subset of the AF3 semantic could be translated to VHDL. And the data types in AF3 are encoded as standardized data types in VHDL(SIGNED and UNSIGNED in IEEE.NUMERIC_STD package).
For example, the "division" operator is not synthesizable in most of the well known VHDL synthesis software. If you want use AF3 VHDL code generator, you should not use "/" operator in your design.
The subset of AF3 semantic, which is supported from VHDL code generator, will be listed in the table 1. Currently, the VHDL code generator supports component and component specifications for atomic component(Code specification, state automaton and mode automaton).
Combing with the test model of AF3, the testbench for target design could be generated at the same time. Then you can import the generated codes in ModelSim or Xilinx ISE and run the simulation. Simulation behavior in such VHDL simulators and AF3 simulator are identical.
Combining with the test model of AF3, the testbench for target design could be generated at the same time. Then you can import the generated codes in ModelSim or Xilinx ISE and run the simulation. Simulation behavior in such VHDL simulators and AF3 simulator are identical.
A step in AF3 simulator corresponds one clock in VHDL Simulator. If the simulation result is optimal, you can synthesize the generated VHDL files(you need here some constraint files) and generate hardware level design for FPGA.
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<br> Table 1: The AF3 semantic supported by VHDL generator
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<h4><font color="#336699">Preference Setting for VHDL Generator</font></h4>
There is a preference page for VHDL generator, where you can set, whether the VHDL testbench file should be generated together with the design. By default is this option selected.
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<img src="./pictures/VHDL.Preference.png">
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<h4><font color="#336699">How To Generate VHDL Code</font></h4>
The VHDL generation process is very similar with C code generator. You can start the code generation by using the context menu of the component architecture, and click "Run VHDL Code Generator".
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