Commit d0db9169 authored by Mingjun Li's avatar Mingjun Li
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help document for VHDL generator

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Documentation of Generating VHDL Code.
@author li
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<title>Generating VHDL code for the component architecture from AutoFOCUS3 (AF3)</title>
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<h2><u><font color="#336699">Generating synthesizable VHDL Code for Component Architecture</font></u></h2>
<h4><font color="#336699">Introduction</font></h4>
AF3 supports VHDL code generation of component architectures(Deployment is currently not supported.). The generated VHDL codes can be simulated in the <a href="http://www.model.com"><i>ModelSim</i></a> and
<a href="http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm"><i>Xilinx ISE</i></a>. One of the advantages of our VHDL generator is synthesizability of the generated code. That means, the generated codes should be able to
deployed on a FPGA device.
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Because of the limitation of the synthesis only the subset of the AF3 semantic could be translated to VHDL. And the data types in AF3 are encoded as standardized data types in VHDL(SIGNED and UNSIGNED in IEEE.NUMERIC_STD package).
For example, the "division" operator is not synthesizable in most of the well known VHDL synthesis software. If you want use AF3 VHDL code generator, you should not use "/" operator in your design.
The subset of AF3 semantic, which is supported from VHDL code generator, will be listed in the table 1. Currently, the VHDL code generator supports component and component specifications for atomic component(Code specification, state automaton and mode automaton).
Combing with the test model of AF3, the testbench for target design could be generated at the same time. Then you can import the generated codes in ModelSim or Xilinx ISE and run the simulation. Simulation behavior in such VHDL simulators and AF3 simulator are identical.
A step in AF3 simulator corresponds one clock in VHDL Simulator. If the simulation result is optimal, you can synthesize the generated VHDL files(you need here some constraint files) and generate hardware level design for FPGA.
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<table border="1" cellpadding="5" cellspacing="5" width="100%">
<tr>
<th>AF3 element</th>
<th>Support</th>
<th>Comment</th>
</tr>
<tr>
<td width="20%">Specification</td><td width="10%">Yes</td><td> Code Specification, State Automaton, Mode Automaton </td>
</tr>
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<td width="20%">Operator</td><td width="10%">Yes</td><td> +, -, *, and, or, not, &gt;, &gt;=, =, &lt;, &lt;=, != <font color="red">(Notice: "/" is not supported)</font> </td>
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<td width="20%">Type</td><td width="10%">Yes</td><td> int(VHDL type: signed(31 downto 0)), boolean(VHDL type: boolean) </td>
</tr>
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<td width="20%">User defined Function</td><td width="10%">No</td><td> - </td>
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<td width="20%">User defined Enumeration</td><td width="10%">No</td><td> - </td>
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</table>
<br> Table 1: The AF3 semantic supported by VHDL generator
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<h4><font color="#336699">How To Generate VHDL Code</font></h4>
The VHDL generation process is very similar with C code generator. You can start the code generation by using the context menu of the component architecture, and click "Run VHDL Code Generator".
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<img src="./pictures/VHDL.Code.Generation.Start.png">
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After that you can select a target folder, which is to be in the Eclipse workspace dictionary.
(Please use the Storage-Perspective to create Eclipse workspace projects and folders.
If you don't already have the Storage-Perspective, you can add it by pressing the
<img src="./pictures/VHDL.Select.Target.Folder.png"> button near to the Perspective buttons, select "Other..." and then select "Storage".).
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<img src="./pictures/Code.Generation.Select.png">
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Once the code generation is complete, you can find the result in the Storage-Perspective. All files are stored in "VHDL-gen" folder.
The following picture shows the result of the component architecture generation.
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<img src="./pictures/VHDL.Code.Generation.Storage.View.png">
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Now, we have done the generation job completely. The next chapter will show you, how to import and simulate the codes in a VHDL simulator.
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<h4><font color="#336699">Import and Simulate the VHDL Code</font></h4>
In this tutorial we use the Xilinx ISE to simulate VHDL code. This software has free edition named "ISE WebPACK" and the version is 12.4. For more detail information about this software you can go to its homepage.
After start the application, you need a project to store the VHDL codes, if you don't have one, then you should create a new project in "start" window, as illustrated in following picture.
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<img src="./pictures/VHDL.ISE.create.project.png">
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After some configuration steps we will get a empty project. Now we can import the generated codes in to this project. By select "Add Copy of Source" Button in "design" window, you can import the code from the computer.
Select all generated vhd-files and then click "OK". Then a popup windows should be appeared. We should select the association for each file in this window. Notice: if we have a testbench file in the generated files, we must selct the "simulation"
in association colum(See following figure).
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<img src="./pictures/VHDL.ISE.add.source.copy.png">
<img src="./pictures/VHDL.ISE.select.association.png">
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Now project is simulatable, if you have a testbench file in the project. Switch to "Simulation" view, and select the testbench file, which should be simulated. Then double click "Simulate Behavioral Model".
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<img src="./pictures/VHDL.ISE.simulate.view.png">
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As result a new windows is appeared and the the simulation result should looks like in the following figure.
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<img src="./pictures/VHDL.ISE.Wave.PNG">
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