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Commit f3c11820 authored by Li's avatar Li
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new parameter in VHDL generator preference page and update for helper docu. 

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parent 5c4bf32c
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org.fortiss.af3.rcp.application/trunk/html/vhdl_code_generation.html
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@author li
@author $Author$
@version $Rev$
@ConQAT.Rating YELLOW Hash: 0CCD946787BCF8660CECA34E410F3612
@ConQAT.Rating YELLOW Hash: 641E5FA40D0E187148654FB96A12E8A3
-->
<html>
......@@ -51,7 +51,7 @@ A step in AF3 simulator corresponds one clock in VHDL Simulator. If the simulati
<td width="20%">User defined Function</td><td width="5%">No</td><td> - </td>
</tr>
<tr>
<td width="20%">User defined Enumeration</td><td width="5%">No</td><td> - </td>
<td width="20%">User defined Enumeration</td><td width="5%">Yes</td><td> Synthesis supports the enumeration type. </td>
</tr>
</table>
<br> Table 1: The AF3 semantic supported by VHDL generator
......@@ -59,7 +59,7 @@ A step in AF3 simulator corresponds one clock in VHDL Simulator. If the simulati
<br><br>
<h4><font color="#336699">Preference Setting for VHDL Generator</font></h4>
There is a preference page for VHDL generator, where you can set, whether the VHDL testbench file should be generated together with the design. By default is this option selected.
There is a preference page for VHDL generator, where you can set, whether the VHDL testbench file should be generated together with the design. By default is this option selected. And the clock period used by testbench can be specified, too.
<br><br>
<img src="./pictures/VHDL.Preference.png">
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