Junit tests for vhdl generator

refs 662

org.fortiss.af3.generator.common/trunk/src/org/fortiss/af3/generator/common/model/vhdl/VHDL64BitInt.java

@@ -17,7 +17,6 @@ $Id$
 +--------------------------------------------------------------------------*/
 package org.fortiss.af3.generator.common.model.vhdl;
 
-import org.fortiss.af3.project.model.typesystem.IType;
 import org.fortiss.af3.project.model.typesystem.impl.ITypeImpl;
 
 /**
@@ -26,7 +25,7 @@ import org.fortiss.af3.project.model.typesystem.impl.ITypeImpl;
  * @author li
  * @author $Author$
  * @version $Rev$
- * @ConQAT.Rating GREEN Hash: 160B3F41BD3CCDC190BA807814588ED1
+ * @ConQAT.Rating YELLOW Hash: F0915768C92CA78EBA364C16C4AA9BEF
  */
 public class VHDL64BitInt extends ITypeImpl {
 
@@ -44,7 +43,7 @@ public class VHDL64BitInt extends ITypeImpl {
 	}
 
 	/** Creates BaseType instance with the given identifier. */
-	public static IType create(String identifier) {
+	public static VHDL64BitInt create(String identifier) {
 		VHDL64BitInt result = new VHDL64BitInt();
 		result.setName(identifier);
 		return result;