[Analyses/Simulation] Looping simulations
Step-by-step to get to the situation:
- open the attached model
- go to the “A/G, Contracts, Patterns” aspect of the component in the component architecture
- check the only specification atom
- it should be FAIL and the trace should be now displaying in the “Counterexample Viewer” view
- observe (reading the text) how the counter-example is made a first state and then another state looping on itself
- then click “Open Simulator” to open the counter-example in the simulator
- run the simulator
What happens:
- after two steps you get to the end of the simulation (Pop-up “Couterexample simulation ended”, “Start from the beginning”)
Expected:
- a pop-up indicating the end of the loop
- the simulation automatically goes back at the beginning of the loop, not at the beginning of the simulation
(from redmine: issue id 2128, created on 2014-09-05)
- Relations:
- relates #2165 (closed)
- Uploads: