Hier. Platform: Switch between Power-/ClockIn and -Out types at layer borders
Power and Clock Ports are used to model the power and clock distribution
within embedded systems. Therefore, they must be able to pass through
layers to model different “clock/power domains” of chips or devices.
Currently, if a Power-/ClockIn is added to some (let’s say) node, it also appears as a Power-/ClockIn at the lower layer but cannot be connected to any contained elements. Thus, the related compositors must be adapter for this use case.
Adjust the corresponding compositors to account for the use case described above. Eventually use directed connections to model the “top-down characteristics”.
(from redmine: issue id 3981, created on 2020-03-30, closed on 2020-04-02)