Commit ced48adb authored by Dorel Coman's avatar Dorel Coman Committed by Oliver Horst
Browse files

memguard: improved idention. Added documentation in freertos/doc

parent ffacc859
This diff is collapsed.
......@@ -96,7 +96,7 @@
*/
static inline void pmu_enable_counter(uint32_t idx)
{
write_register(PMCNTENSET_EL0, (1 << idx));
write_register(PMCNTENSET_EL0, (1 << idx));
}
/**
......@@ -105,7 +105,7 @@ static inline void pmu_enable_counter(uint32_t idx)
*/
static inline void pmu_disable_counter(uint32_t idx)
{
write_register(PMCNTENSET_EL0, (0 << idx));
write_register(PMCNTENSET_EL0, (0 << idx));
}
/**
......@@ -114,9 +114,9 @@ static inline void pmu_disable_counter(uint32_t idx)
*/
static inline void pmu_control_write(uint32_t val)
{
val &= PMCR_MASK;
isb();
write_register(PMCR_EL0, val);
val &= PMCR_MASK;
isb();
write_register(PMCR_EL0, val);
}
/**
......@@ -125,9 +125,9 @@ static inline void pmu_control_write(uint32_t val)
*/
static inline uint32_t pmu_control_read(void)
{
unsigned int val;
read_register(PMCR_EL0, val);
return val;
unsigned int val;
read_register(PMCR_EL0, val);
return val;
}
/**
......@@ -137,8 +137,8 @@ static inline uint32_t pmu_control_read(void)
*/
static inline void set_pmcr_el0()
{
uint32_t val = pmu_control_read();
pmu_control_write(val | PMCR_E);
uint32_t val = pmu_control_read();
pmu_control_write(val | PMCR_E);
}
......@@ -149,8 +149,8 @@ static inline void set_pmcr_el0()
*/
static inline void pmu_counter_select(uint32_t idx)
{
write_register(PMSELR_EL0, idx);
isb();
write_register(PMSELR_EL0, idx);
isb();
}
/**
......@@ -162,8 +162,8 @@ static inline void pmu_counter_select(uint32_t idx)
*/
static inline void pmu_counter_set_event_type(uint32_t idx, uint32_t type)
{
pmu_counter_select(idx);
write_register(PMXEVTYPER_EL0, type);
pmu_counter_select(idx);
write_register(PMXEVTYPER_EL0, type);
}
void pmu_init_counters()
......@@ -174,115 +174,115 @@ void pmu_init_counters()
}
#endif
set_pmcr_el0();
set_pmcr_el0();
uint32_t number_of_counters = pmu_get_number_counters();
for (uint32_t i = 0; i < number_of_counters; ++i) {
pmu_clear_interrupt(i);
}
uint32_t number_of_counters = pmu_get_number_counters();
for (uint32_t i = 0; i < number_of_counters; ++i) {
pmu_clear_interrupt(i);
}
}
void pmu_enable_counter_for_event(uint32_t idx, uint32_t event_type)
{
pmu_disable_counter(idx);
pmu_counter_set_event_type(idx, event_type);
pmu_enable_counter(idx);
pmu_disable_counter(idx);
pmu_counter_set_event_type(idx, event_type);
pmu_enable_counter(idx);
}
uint32_t pmu_get_core_id()
{
uint32_t value;
read_register(MPIDR_EL1, value);
value = value & CPU_ID_MASK;
uint32_t value;
read_register(MPIDR_EL1, value);
value = value & CPU_ID_MASK;
return value;
return value;
}
uint32_t pmu_counter_has_overflowed(uint32_t idx)
{
uint32_t value;
read_register(PMOVSSET_EL0, value);
uint32_t value;
read_register(PMOVSSET_EL0, value);
return ((value) & (1 << idx));
return ((value) & (1 << idx));
}
void pmu_enable_intr(uint32_t idx)
{
write_register(PMINTENSET_EL1, (1 << idx));
write_register(PMINTENSET_EL1, (1 << idx));
}
void pmu_disable_intr(uint32_t idx)
{
/* Disabling the interrupt for the selected counter */
write_register(PMINTENCLR_EL1, (1 << idx));
isb();
/* Disabling the interrupt for the selected counter */
write_register(PMINTENCLR_EL1, (1 << idx));
isb();
/* Clearing the interrupt line */
write_register(PMOVSCLR_EL0, (1 << idx));
isb();
/* Clearing the interrupt line */
write_register(PMOVSCLR_EL0, (1 << idx));
isb();
}
void pmu_clear_interrupt(uint32_t idx)
{
write_register(PMOVSCLR_EL0, (1 << idx));
isb();
write_register(PMOVSCLR_EL0, (1 << idx));
isb();
}
void pmu_start_counter(uint32_t idx, uint32_t count_val)
{
/* Writing the value on the selected counter */
pmu_write_counter(idx, count_val);
/* Writing the value on the selected counter */
pmu_write_counter(idx, count_val);
/* Clear the interrupt register before enabling it again to be sure it
wasn't already triggered */
pmu_clear_interrupt(idx);
pmu_enable_intr(idx);
/* Clear the interrupt register before enabling it again to be sure it
wasn't already triggered */
pmu_clear_interrupt(idx);
pmu_enable_intr(idx);
}
uint32_t mask_value(uint32_t value)
{
uint32_t MAX = 0xFFFFFFFF;
uint32_t val = MAX - value;
uint32_t MAX = 0xFFFFFFFF;
uint32_t val = MAX - value;
return val;
return val;
}
uint32_t pmu_read_counter(uint32_t idx)
{
uint32_t value;
uint32_t value;
if (idx < pmu_get_number_counters()) {
pmu_counter_select(idx);
read_register(PMXEVCNTR_EL0, value);
if (idx < pmu_get_number_counters()) {
pmu_counter_select(idx);
read_register(PMXEVCNTR_EL0, value);
return value;
} else {
return 0;
}
return value;
} else {
return 0;
}
}
void pmu_write_counter(uint32_t idx, uint32_t value)
{
if (idx < pmu_get_number_counters()) {
pmu_counter_select(idx);
write_register(PMXEVCNTR_EL0, value);
}
if (idx < pmu_get_number_counters()) {
pmu_counter_select(idx);
write_register(PMXEVCNTR_EL0, value);
}
}
uint64_t pmu_read_cycle_counter(void)
{
uint64_t value;
read_register(PMCCNTR_EL0, value);
return value;
uint64_t value;
read_register(PMCCNTR_EL0, value);
return value;
}
uint32_t pmu_get_number_counters(void)
{
uint32_t count = pmu_control_read();
/* Extracting the bits[15:11] - These bits store the number of counters
available for the respective CPU. The description of the register can be
found in the A53 CPU Technical Reference Manual at the chapter 12.4.1
Performance Monitors Control Register */
count = ((count >> PMCR_N_SHIFT) & PMCR_N_MASK);
return count;
uint32_t count = pmu_control_read();
/* Extracting the bits[15:11] - These bits store the number of counters
available for the respective CPU. The description of the register can be
found in the A53 CPU Technical Reference Manual at the chapter 12.4.1
Performance Monitors Control Register */
count = ((count >> PMCR_N_SHIFT) & PMCR_N_MASK);
return count;
}
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