Commit e60d9f1c authored by Dorel Coman's avatar Dorel Coman Committed by Oliver Horst
Browse files

memguard: improved idention

parent b13d5fc0
This diff is collapsed.
......@@ -13,21 +13,21 @@
#define write_register(REG, VAL) __asm__ __volatile__("msr " #REG ",%0" : : "r" (VAL))
/* Mask used for extracting the CPU_ID from the MPIDR_EL1 register */
#define CPU_ID_MASK (uint32_t) (0xFF)
#define CPU_ID_MASK (uint32_t) (0xFF)
/* Macros used for accessing and setting up the PMU registers */
#define PMCR_MASK 0x3f
#define PMCR_E (1 << 0) /* Enable all counters */
#define PMCR_P (1 << 1) /* Reset all counters */
#define PMCR_C (1 << 2) /* Cycle counter reset */
#define PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
#define PMCR_N_SHIFT 11 /* Mask used for getting Number of counters supported */
#define PMCR_N_MASK 0x1f
#define PMCR_MASK 0x3f
#define PMCR_E (1 << 0) /* Enable all counters */
#define PMCR_P (1 << 1) /* Reset all counters */
#define PMCR_C (1 << 2) /* Cycle counter reset */
#define PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
#define PMCR_N_SHIFT 11 /* Mask used for getting Number of counters supported */
#define PMCR_N_MASK 0x1f
#define PMU_USERENR_MASK 0xf /* Mask for writable bits */
#define PMUSERENR_EN_EL0 (1 << 0) /* EL0 access enable */
#define PMUSERENR_CR (1 << 2) /* Cycle counter read enable */
#define PMUSERENR_ER (1 << 3) /* Event counter read enable */
#define PMUSERENR_ENABLE_ALL 0xD
#define PMUSERENR_EN_EL0 (1 << 0) /* EL0 access enable */
#define PMUSERENR_CR (1 << 2) /* Cycle counter read enable */
#define PMUSERENR_ER (1 << 3) /* Event counter read enable */
#define PMUSERENR_ENABLE_ALL 0xD
/*********************************************************
* Registers of the Performance Monitor Unit (PMU)
......@@ -79,10 +79,10 @@
*/
static inline void enable_user_access_to_counters()
{
uint32_t reg_val;
read_register(PMUSERENR_EL0, reg_val);
reg_val = reg_val | PMUSERENR_ENABLE_ALL;
write_register(PMUSERENR_EL0, reg_val);
uint32_t reg_val;
read_register(PMUSERENR_EL0, reg_val);
reg_val = reg_val | PMUSERENR_ENABLE_ALL;
write_register(PMUSERENR_EL0, reg_val);
}
/**
......@@ -93,7 +93,7 @@ static inline void enable_user_access_to_counters()
*/
static inline void pmu_enable_counter(uint32_t idx)
{
write_register(PMCNTENSET_EL0, (1 << idx));
write_register(PMCNTENSET_EL0, (1 << idx));
}
/**
......@@ -102,7 +102,7 @@ static inline void pmu_enable_counter(uint32_t idx)
*/
static inline void pmu_disable_counter(uint32_t idx)
{
write_register(PMCNTENSET_EL0, (0 << idx));
write_register(PMCNTENSET_EL0, (0 << idx));
}
/**
......@@ -111,9 +111,9 @@ static inline void pmu_disable_counter(uint32_t idx)
*/
static inline void pmu_control_write(uint32_t val)
{
val &= PMCR_MASK;
isb();
write_register(PMCR_EL0, val);
val &= PMCR_MASK;
isb();
write_register(PMCR_EL0, val);
}
/**
......@@ -122,9 +122,9 @@ static inline void pmu_control_write(uint32_t val)
*/
static inline uint32_t pmu_control_read(void)
{
unsigned int val;
read_register(PMCR_EL0, val);
return val;
unsigned int val;
read_register(PMCR_EL0, val);
return val;
}
/**
......@@ -134,8 +134,8 @@ static inline uint32_t pmu_control_read(void)
*/
static inline void set_pmcr_el0()
{
uint32_t val = pmu_control_read();
pmu_control_write(val | PMCR_E);
uint32_t val = pmu_control_read();
pmu_control_write(val | PMCR_E);
}
......@@ -146,8 +146,8 @@ static inline void set_pmcr_el0()
*/
static inline void pmu_counter_select(uint32_t idx)
{
write_register(PMSELR_EL0, idx);
isb();
write_register(PMSELR_EL0, idx);
isb();
}
/**
......@@ -159,8 +159,8 @@ static inline void pmu_counter_select(uint32_t idx)
*/
static inline void pmu_type_select(uint32_t idx, uint32_t type)
{
pmu_counter_select(idx);
write_register(PMXEVTYPER_EL0, type);
pmu_counter_select(idx);
write_register(PMXEVTYPER_EL0, type);
}
void pmu_init_counters()
......@@ -176,9 +176,9 @@ void pmu_init_counters()
void pmu_enable_counter_for_event(uint32_t idx, uint32_t event_type)
{
pmu_disable_counter(idx);
pmu_type_select(idx, event_type);
pmu_enable_counter(idx);
pmu_disable_counter(idx);
pmu_type_select(idx, event_type);
pmu_enable_counter(idx);
}
uint32_t pmu_get_core_id()
......@@ -192,10 +192,10 @@ uint32_t pmu_get_core_id()
uint32_t pmu_counter_has_overflowed(uint32_t idx)
{
uint32_t value;
read_register(PMOVSSET_EL0, value);
uint32_t value;
read_register(PMOVSSET_EL0, value);
return ((value) & (1 << idx));
return ((value) & (1 << idx));
}
void pmu_enable_intr(uint32_t idx)
......@@ -222,11 +222,11 @@ void pmu_clear_interrupt(uint32_t idx)
void pmu_start_counter(uint32_t idx, uint32_t count_val)
{
/* Writing the value on the selected counter */
/* Writing the value on the selected counter */
pmu_write_counter(idx, count_val);
/* Clear the interrupt register before enabling it again to be sure it
wasn't already triggered */
/* Clear the interrupt register before enabling it again to be sure it
wasn't already triggered */
pmu_clear_interrupt(idx);
pmu_enable_intr(idx);
}
......@@ -273,9 +273,9 @@ uint32_t pmu_get_number_counters(void)
{
uint32_t count = pmu_control_read();
/* Extracting the bits[15:11] - These bits store the number of counters
available for the respective CPU. The description of the register can
be found in the A53 CPU Technical Reference Manual at the chapter
12.4.1 Performance Monitors Control Register */
available for the respective CPU. The description of the register can be
found in the A53 CPU Technical Reference Manual at the chapter 12.4.1
Performance Monitors Control Register */
count = ((count >> PMCR_N_SHIFT) & PMCR_N_MASK);
return count;
}
\ No newline at end of file
......@@ -84,19 +84,16 @@ static struct ipi_info chn_ipi_info[] = {
#if (MASTER_CORE == 1)
const struct firmware_info fw_table[] =
{
{"rpc",
(unsigned long)(void *)&_binary_amp_remote_elf_start,
(unsigned long)(void *)&_binary_amp_remote_elf_end
},
};
{
{"rpc",
(unsigned long)(void *)&_binary_amp_remote_elf_start,
(unsigned long)(void *)&_binary_amp_remote_elf_end},
};
#else
const struct firmware_info fw_table[] =
{
{"rpc",
0,
0},
};
{
{"rpc", 0, 0},
};
#endif
const int fw_table_size = sizeof(fw_table)/sizeof(struct firmware_info);
......
......@@ -9,8 +9,7 @@
#define RPMSG_CHAN_NAME "rpmsg-openamp-demo-channel"
#if(MASTER_CORE == 1)
/* Firmware table and binary remoteproc firmware symbols.
*/
/* Firmware table and binary remoteproc firmware symbols. */
extern unsigned char _binary_amp_remote_elf_start;
extern unsigned char _binary_amp_remote_elf_end;
#endif
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment