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toki
components
freertos-portable
Commits
1751b72a
Commit
1751b72a
authored
Jan 30, 2020
by
Johannes Wiesboeck
Committed by
Oliver Horst
Aug 15, 2020
Browse files
[chg] Make stm macros 'header-only'.
parent
277961fa
Changes
2
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GCC/ARM_CA53_64_BIT/include/freertos+/coresight/stm_trace.h
View file @
1751b72a
...
...
@@ -2,6 +2,7 @@
#define FREERTOSPLUS_CORESIGHT_STM_TRACE_H
#include
"xil/xil_io.h"
#include
"xil/csparameters.h"
#if !defined (__aarch64__)
#error "Unsupported Processor Type"
...
...
@@ -19,10 +20,10 @@
*
* A possible use of these macros could look like this: STM_TRACE_8(0, G_DMTS, 42);
*/
#define STM_TRACE_8(port, type, data) Xil_Out8( &
xSTMTraceDrvData.axi
->ports[port].type, data )
#define STM_TRACE_16(port, type, data) Xil_Out16( &
xSTMTraceDrvData.axi
->ports[port].type, data )
#define STM_TRACE_32(port, type, data) Xil_Out32( &
xSTMTraceDrvData.axi
->ports[port].type, data )
#define STM_TRACE_64(port, type, data) Xil_Out64( &
xSTMTraceDrvData.axi
->ports[port].type, data )
#define STM_TRACE_8(port, type, data) Xil_Out8( &
((stm_axi_t *)( CS_STM_AXI_BASE ))
->ports[port].type, data )
#define STM_TRACE_16(port, type, data) Xil_Out16( &
((stm_axi_t *)( CS_STM_AXI_BASE ))
->ports[port].type, data )
#define STM_TRACE_32(port, type, data) Xil_Out32( &
((stm_axi_t *)( CS_STM_AXI_BASE ))
->ports[port].type, data )
#define STM_TRACE_64(port, type, data) Xil_Out64( &
((stm_axi_t *)( CS_STM_AXI_BASE ))
->ports[port].type, data )
/*******************************************************************************
...
...
GCC/ARM_CA53_64_BIT/src/freertos+/coresight/stm_trace.c
View file @
1751b72a
...
...
@@ -22,7 +22,6 @@
#include
"freertos+/coresight/stm_trace.h"
#include
"xil/xil_io.h"
#include
"xil/csparameters.h"
#include
<stdio.h>
...
...
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