Commit 3cd4d108 authored by Johannes Wiesboeck's avatar Johannes Wiesboeck Committed by Oliver Horst
Browse files

[chg] Adapted to CPU mask change in cpu.h

parent 1751b72a
......@@ -12,17 +12,15 @@
/* Mask used for extracting the CPU_ID from the MPIDR_EL1 register */
#define ARM_CA53_CPU_ID_MASK ( (UBaseType_t)( 0xFFu ) )
extern volatile uint64_t ulCpuBarrierMask1;
extern volatile uint64_t ulCpuBarrierMask2;
static volatile uint64_t __attribute__((section (".ocm_ram"))) ulCpuBarrierMask1 = ( (uint64_t)__AMP_CORE_MASK );
static volatile uint64_t __attribute__((section (".ocm_ram"))) ulCpuBarrierMask2 = 0;
inline void vHalCpuWaitForEvent()
static inline void vHalCpuWaitForEvent()
{
__asm__("wfe");
}
inline void vHalCpuSignalEvent()
static inline void vHalCpuSignalEvent()
{
__asm__("sev");
}
......@@ -39,10 +37,10 @@ UBaseType_t uxCpuId;
void vHalCpuBarrier()
{
uint64_t mask1;
uint64_t mask2;
uint64_t mask1;
uint64_t mask2;
UBaseType_t uxCpuId = uxHalGetCpuId();
UBaseType_t uxCpuId = uxHalGetCpuId();
/* We disable interrupts here to ensure that nothing distracts the
* synchronization of the cores. */
......@@ -61,7 +59,7 @@ UBaseType_t uxCpuId = uxHalGetCpuId();
* cores again. */
while ( 1 )
{
if ( atomic_load( &ulCpuBarrierMask1 ) ^ mask2 != ( (uint64_t)__AMP_CORE_MASK ) )
if ( atomic_load( &ulCpuBarrierMask1 ) ^ mask2 != ( AMP_CORE_MASK_U64 ) )
{
vHalCpuWaitForEvent();
}
......@@ -93,7 +91,7 @@ UBaseType_t uxCpuId = uxHalGetCpuId();
* again. */
while ( 1 )
{
if ( mask1 ^ atomic_load( &ulCpuBarrierMask2 ) != ( (uint64_t)__AMP_CORE_MASK ) )
if ( mask1 ^ atomic_load( &ulCpuBarrierMask2 ) != ( AMP_CORE_MASK_U64 ) )
{
vHalCpuWaitForEvent();
}
......
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