Commit 4dbec35b authored by Oliver Horst's avatar Oliver Horst
Browse files

[chg] Moved hal component out and replaced libc dependencies

- Replaced stdlib.h with stddef.h
- Moved drivers to toki-hal-port
- Added dependency to toki-libc-headers and toki-perfmon
parent f4ca2ef8
......@@ -6,7 +6,7 @@ find_package(
)
get_target_property(
CONFIG_DEFINES
CONFIG_DEFINES
freertos-config
INTERFACE_COMPILE_DEFINITIONS
)
......
......@@ -21,6 +21,16 @@ find_package(
REQUIRED
)
find_package(
toki-libc-headers 0.1
REQUIRED
)
find_package(
toki-perfmon 0.1
REQUIRED
)
add_library(
freertos-portable
......@@ -34,6 +44,8 @@ target_link_libraries(
#
PRIVATE freertos-headers
xil-headers
toki-libc-headers
toki-perfmon
)
target_include_directories(
......
......@@ -4,8 +4,10 @@ include(CMakeFindDependencyMacro)
find_dependency(freertos-headers)
find_dependency(xil-headers)
find_dependency(toki-hal)
find_dependency(toki-perfmon)
# Import targets
include(${CMAKE_CURRENT_LIST_DIR}/freertos-portable-targets.cmake)
check_required_components(freertos-plus)
check_required_components(freertos-portable)
/******************************************************************************
* Created by Dorel Coman on 23.10.17.
*
* This file contains all the events which can be monitored by Performance
* Monitor Unit (PMU) for each core. The perfmon.c API provided can be used to
* monitor these events and trigger and interrupt when a certain
* event is occurring for a certain amount of times.
*
* With the function pmu_type_select() inside perfmon.c one can choose which
* of the following events to monitor.
*
* For a better description of the events check the paragraph "12.9 Events"
* in the technical reference manual of the
* ARM Cortex-A53
*
* Following list is taken from:
* https://elixir.bootlin.com/linux/v4.0/source/arch/arm64/kernel/perf_event.c
******************************************************************************/
#ifndef FREERTOS_EXTRA_PERFMON_ARCH_ARM_CA53_EVENTS_H
#define FREERTOS_EXTRA_PERFMON_ARCH_ARM_CA53_EVENTS_H
#define PERFMON_PERFCTR_PMNC_SW_INCR 0x00
#define PERFMON_PERFCTR_L1_DCACHE_REFILL 0x03
#define PERFMON_PERFCTR_L1_DCACHE_ACCESS 0x04
#define PERFMON_PERFCTR_PC_BRANCH_MIS_PRED 0x10
#define PERFMON_PERFCTR_CLOCK_CYCLES 0x11
#define PERFMON_PERFCTR_PC_BRANCH_PRED 0x12
#define PERFMON_PERFCTR_INSTR_EXECUTED 0x08
#define PERFMON_PERFCTR_OP_SPEC 0x1B
#define PERFMON_PERFCTR_MEM_READ 0x06
#define PERFMON_PERFCTR_MEM_WRITE 0x07
#define PERFMON_PERFCTR_EXC_TAKEN 0x09
#define PERFMON_PERFCTR_EXC_EXECUTED 0x0A
#define PERFMON_PERFCTR_CID_WRITE 0x0B
#define PERFMON_PERFCTR_PC_WRITE 0x0C
#define PERFMON_PERFCTR_PC_IMM_BRANCH 0x0D
#define PERFMON_PERFCTR_PC_PROC_RETURN 0x0E
#define PERFMON_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
#define PERFMON_PERFCTR_TTBR_WRITE 0x1C
#define PERFMON_PERFCTR_CHAIN 0x1E
#define PERFMON_PERFCTR_BR_RETIRED 0x21
#define PERFMON_PERFCTR_L1_ICACHE_REFILL 0x01
#define PERFMON_PERFCTR_ITLB_REFILL 0x02
#define PERFMON_PERFCTR_DTLB_REFILL 0x05
#define PERFMON_PERFCTR_MEM_ACCESS 0x13
#define PERFMON_PERFCTR_L1_ICACHE_ACCESS 0x14
#define PERFMON_PERFCTR_L1_DCACHE_WB 0x15
#define PERFMON_PERFCTR_L2_CACHE_ACCESS 0x16
#define PERFMON_PERFCTR_L2_CACHE_REFILL 0x17
#define PERFMON_PERFCTR_L2_CACHE_WB 0x18
#define PERFMON_PERFCTR_BUS_ACCESS 0x19
#define PERFMON_PERFCTR_MEM_ERROR 0x1A
#define PERFMON_PERFCTR_BUS_CYCLES 0x1D
#define PERFMON_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
#define PERFMON_PERFCTR_L2D_CACHE_ALLOCATE 0x20
#define PERFMON_PERFCTR_BR_MIS_PRED_RETIRED 0x22
#define PERFMON_PERFCTR_STALL_FRONTEND 0x23
#define PERFMON_PERFCTR_STALL_BACKEND 0x24
#define PERFMON_PERFCTR_L1D_TLB 0x25
#define PERFMON_PERFCTR_L1I_TLB 0x26
#define PERFMON_PERFCTR_L2I_CACHE 0x27
#define PERFMON_PERFCTR_L2I_CACHE_REFILL 0x28
#define PERFMON_PERFCTR_L3D_CACHE_ALLOCATE 0x29
#define PERFMON_PERFCTR_L3D_CACHE_REFILL 0x2A
#define PERFMON_PERFCTR_L3D_CACHE 0x2B
#define PERFMON_PERFCTR_L3D_CACHE_WB 0x2C
#define PERFMON_PERFCTR_L2D_TLB_REFILL 0x2D
#define PERFMON_PERFCTR_L21_TLB_REFILL 0x2E
#define PERFMON_PERFCTR_L2D_TLB 0x2F
#define PERFMON_PERFCTR_L21_TLB 0x30
#define PERFMON_PERFCTR_PREFETCH_LINEFILL 0xC2
#endif /* FREERTOS_EXTRA_PERFMON_ARCH_ARM_CA53_EVENTS_H */
#ifndef FREERTOS_EXTRA_PERFMON_ARCH_ARM_CA53_PLATFORM_H
#define FREERTOS_EXTRA_PERFMON_ARCH_ARM_CA53_PLATFORM_H
/* This ID has to be used, when managing the Cycle Counter (PMCCNTR_EL0) is
and it is wanted to access some functions related like the followings:
vPerfmonEnableInterruptForCounter(), vPerfmonDisableInterruptForCounter(),
vPerfmonClearInterruptForCounter().
The define represents the bit on the following registers which has to be used
in order to manipulate the PMCCNTR_EL0: PMINTENCLR_EL1, PMINTENSET_EL1,
PMOVSCLR_EL0, PMOVSSET_EL0.
For more details please read the description of the registers in the ARMv8
Technical Reference Manual between the chapters D10.4.10 and D10.4.13 (Pag.
2866 - 2873) which can be found at the link:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf */
#define PERFMON_CYLCE_CNTR_ID 31U
/* The number of PMU counters available on each core of the cluster Cortex-A53 */
#define PERFMON_NUMBER_OF_COUNTERS 6U
#endif /* FREERTOS_EXTRA_PERFMON_ARCH_ARM_CA53_PLATFORM_H */
cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
add_subdirectory(hal)
add_subdirectory(memguard)
add_subdirectory(perfmon)
add_subdirectory(stdlib)
cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
target_sources(
freertos-portable
#
PRIVATE
"${CMAKE_CURRENT_LIST_DIR}/cpu.c"
)
add_subdirectory(drivers)
BSD with Attribution License
Copyright (c) 2015-2020 fortiss GmbH - Research Institute of the
Free State of Bavaria, Guerickestr. 25, 80805 Munich, Germany
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
3. Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
4. Redistributions of any form whatsoever must retain the following
acknowledgment: 'This product includes software developed by the
fortiss GmbH -- Research Institute of the Free State of Bavaria,
Munich, Germany (https://www.fortiss.org/).'
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SPDX-License-Identifier: BSD-3-Clause-Attribution
#include "freertos/FreeRTOS.h"
#include "freertos+/hal/cpu.h"
#include "xil/xil_cpu.h"
inline UBaseType_t uxHalGetCpuId()
{
return (UBaseType_t)Xil_CpuId();
}
inline void vHalCpuBarrier()
{
Xil_CpuBarrier();
}
cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
target_sources(
freertos-portable
#
PRIVATE
"${CMAKE_CURRENT_LIST_DIR}/uart.c"
"${CMAKE_CURRENT_LIST_DIR}/can.c"
)
This diff is collapsed.
/**
* \file
* \brief UART driver abstraction (platform specific part: xilinx zcu102).
*/
/******************************************************************************/
/*** Includes ***/
/******************************************************************************/
#include "freertos+/hal/drivers/uart.h"
#include "xil/xparameters.h"
#include "xil/drivers/xuartps.h"
/******************************************************************************/
/*** Declarations ***/
/******************************************************************************/
/******************************************************************************/
/*** Defines ***/
/******************************************************************************/
#define MAX_NUM_UART_CONTROLLERS 2U /* Maximum number of supported UART
Controllers */
/******************************************************************************/
/*** Type definitions ***/
/******************************************************************************/
typedef struct
{
BaseType_t isCtrlInit; /* Is the controller already initialized? */
XUartPs uartXilinxInst; /* Instances of Xilinx UART controller */
uint32_t baudrate; /* Requested UART Baud Rate, in bit/s */
}uartInstance_t;
/******************************************************************************/
/*** Variables ***/
/******************************************************************************/
/* Instances of the UART controllers */
static uartInstance_t uartInstance[MAX_NUM_UART_CONTROLLERS];
/******************************************************************************/
/*** Prototypes ***/
/******************************************************************************/
/******************************************************************************/
/*** Implementation ***/
/******************************************************************************/
void hal_uart_setup(void)
{
}
int hal_uart_init_channel(hal_io_handle_t handle, uint32_t baudrate)
{
uartInstance_t *uartInstPtr;
XUartPs *xilUartPtr;
XUartPs_Config *cfgPtr;
uint32_t status;
if ( MAX_NUM_UART_CONTROLLERS <= handle )
{
/* Unsupported handle */
return pdFAIL;
}
else
{
uartInstPtr = & uartInstance[handle];
xilUartPtr = & uartInstPtr->uartXilinxInst;
cfgPtr = XUartPs_LookupConfig( handle );
if ( !cfgPtr )
{
return pdFAIL;
}
else
{
uartInstPtr->uartXilinxInst.Config = *cfgPtr;
}
status = XUartPs_CfgInitialize(
xilUartPtr,
&xilUartPtr->Config,
xilUartPtr->Config.BaseAddress
);
if ( XST_SUCCESS != status )
{
return pdFAIL;
}
else
{
/* Run self-test on the UART controller. */
status = XUartPs_SelfTest( xilUartPtr );
if ( XST_SUCCESS != status )
{
return pdFAIL;
}
else
{
/* Set the baudrate. */
status = XUartPs_SetBaudRate( xilUartPtr, baudrate);
if ( XST_SUCCESS != status )
{
return pdFAIL;
}
/* Store the baudrate, for reconfiguring the controller in case
* of bus-off state. */
uartInstPtr->baudrate = baudrate;
/* Enter Normal Mode. */
XUartPs_SetOperMode(xilUartPtr, XUARTPS_OPER_MODE_NORMAL);
while( XUARTPS_OPER_MODE_NORMAL != XUartPs_GetOperMode(xilUartPtr) );
uartInstPtr->isCtrlInit = pdTRUE;
return pdPASS;
}
}
}
}
int hal_uart_getchar(hal_io_handle_t handle, uint8_t *ch)
{
if ( MAX_NUM_UART_CONTROLLERS <= handle )
{
/* Unsupported handle */
return pdFAIL;
}
else
{
if (pdTRUE == uartInstance[handle].isCtrlInit)
{
*ch = XUartPs_RecvByte(uartInstance[handle].uartXilinxInst.Config.BaseAddress);
return pdPASS;
}
return pdFAIL;
}
}
int hal_uart_getchar_timeout(hal_io_handle_t handle, uint8_t *ch, TickType_t timeout)
{
(void) handle;
(void) *ch;
(void) timeout;
return pdFAIL;
}
int hal_uart_putchar(hal_io_handle_t handle, uint8_t ch)
{
if ( MAX_NUM_UART_CONTROLLERS <= handle )
{
/* Unsupported handle */
return pdFAIL;
}
else
{
if (pdTRUE == uartInstance[handle].isCtrlInit)
{
XUartPs_SendByte(uartInstance[handle].uartXilinxInst.Config.BaseAddress, ch);
return pdPASS;
}
return pdFAIL;
}
}
......@@ -7,8 +7,9 @@
#include "xil/drivers/xttcps.h"
#include "xil/drivers/xscugic.h"
#include "freertos+/hal/cpu.h"
#include "freertos+/perfmon.h"
#include "toki/hal/cpu.h"
#include "toki/perfmon.h"
#include "freertos+/memguard.h"
......
cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
target_sources(
freertos-portable
#
PRIVATE
"${CMAKE_CURRENT_LIST_DIR}/perfmon_arch.c"
)
BSD with Attribution License
Copyright (c) 2015-2020 fortiss GmbH - Research Institute of the
Free State of Bavaria, Guerickestr. 25, 80805 Munich, Germany
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
3. Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
4. Redistributions of any form whatsoever must retain the following
acknowledgment: 'This product includes software developed by the
fortiss GmbH -- Research Institute of the Free State of Bavaria,
Munich, Germany (https://www.fortiss.org/).'
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SPDX-License-Identifier: BSD-3-Clause-Attribution
/*******************************************************************************
* Created by Dorel Coman on 21.10.17.
*
* This API provides functionalities for accessing the Performance Monitor
* Counters (PMU) registers of the ARM64 architectures
******************************************************************************/
#include "freertos/FreeRTOS.h"
#include "freertos+/perfmon.h"
#include "xil/xpseudo_asm.h"
/* Macros used for accessing and setting up the PMU registers */
#define PMCR_MASK 0x3Fu
#define PMCR_E (1u << 0u) /* Enable all counters */
#define PMCR_P (1u << 1u) /* Reset all counters */
#define PMCR_C (1u << 2u) /* Cycle counter reset */
#define PMCR_D (1u << 3u) /* CCNT counts every 64th CPU cycle */
#define PMCR_N_SHIFT 11u /* Mask used for getting Number of counters supported */
#define PMCR_N_MASK 0x1Fu
#define PMU_USERENR_MASK 0xFu /* Mask for writable bits */
#define PMUSERENR_EN_EL0 (1u << 0u) /* EL0 access enable */
#define PMUSERENR_CR (1u << 2u) /* Cycle counter read enable */
#define PMUSERENR_ER (1u << 3u) /* Event counter read enable */
#define PMUSERENR_ENABLE_ALL 0xDu
/*********************************************************
* Registers of the Performance Monitor Unit (PMU)
*********************************************************/
/* Performance Monitors Event Counter Selection Register */
#define PMSELR_EL0 "PMSELR_EL0"
/* Performance Monitors User Enable Register */
#define PMUSERENR_EL0 "PMUSERENR_EL0"
/* Performance Monitors Count Enable Set register */
#define PMCNTENSET_EL0 "PMCNTENSET_EL0"
/* Performance Monitors Control Register */
#define PMCR_EL0 "PMCR_EL0"
/* Performance Monitors Cycle Count Register - 64-bit register */
#define PMCCNTR_EL0 "PMCCNTR_EL0"
/* Performance Monitors Selected Event Count Register */
#define PMXEVCNTR_EL0 "PMXEVCNTR_EL0"
/* Performance Monitors Selected Event Type Register */
#define PMXEVTYPER_EL0 "PMXEVTYPER_EL0"
/* Performance Monitors Interrupt Enable Clear register */
#define PMINTENCLR_EL1 "PMINTENCLR_EL1"
/* Performance Monitors Interrupt Enable Set register */
#define PMINTENSET_EL1 "PMINTENSET_EL1"
/* Performance Monitors Overflow Flag Status Clear Register */
#define PMOVSCLR_EL0 "PMOVSCLR_EL0"
/* Performance Monitors Overflow Flag Status Set register */
#define PMOVSSET_EL0 "PMOVSSET_EL0"
/*******************************************************************************
* Function definitions
******************************************************************************/
#if( INCLUDE_vPerfmonEnableUserAccess == 1 )
/**
* It enables user-mode access (EL0: applications) to counters. It is
* important in order to be able to use the counters in FreeRTOS.
*/
static inline void vPerfmonEnableUserAccess()
{
uint32_t reg_val;
reg_val = mfcp( PMUSERENR_EL0 );
reg_val = reg_val | PMUSERENR_ENABLE_ALL;
mtcp( PMUSERENR_EL0, reg_val );
}
#endif
/**
* This function enables the selected counter in order to make it count. If
* the counter is not enabled, it will not count the occurencies of its
* selected event type
* @idx: The counter n index
*/
static inline void vPerfmonEnableCounter( uint32_t idx )
{
mtcp( PMCNTENSET_EL0, (1u << idx) );
}
/**
* This function disables the selected counter.
* @idx: The counter n index
*/
static inline void vPerfmonDisableCounter( uint32_t idx )
{
mtcp( PMCNTENSET_EL0, (0u << idx) );
}
/**
* This function writes the PMCR register of the PMU
* @param val to be written inside the PMCR register
*/
static inline void prvPerfmonWriteControlRegister( UBaseType_t val )
{
val &= PMCR_MASK;
isb();
mtcp( PMCR_EL0, val );
}
/**
* This function returns the value of the PMCR_EL0 register
* @return PMCR_EL0 value
*/
static inline uint32_t prvPerfmonReadControlRegister( void )
{
return (uint32_t)mfcp( PMCR_EL0 );
}
/**
* This function reads the PMCR_EL0 register and writes it back with the value
* needed in order to activate the PMU counters. The PMCR_E mask enables all
* the counters
*/
static inline void set_pmcr_el0()
{