Commit 514e397e authored by Ulrich Huber's avatar Ulrich Huber Committed by Oliver Horst
Browse files

[fix] Use port methods to interact with GIC

parent b32ced27
......@@ -186,6 +186,35 @@ void vPortEnableInterrupt( uint8_t ucInterruptID );
*/
void vPortDisableInterrupt( uint8_t ucInterruptID );
/**
* Sets the interrupt priority and trigger type for the specificd IRQ source.
*
* @param Int_Id is the IRQ source number to modify
* @param Priority is the new priority for the IRQ source. 0 is highest
* priority, 0xF8(248) is lowest. There are 32 priority levels
* supported with a step of 8. Hence the supported priorities are
* 0, 8, 16, 32, 40 ..., 248.
* @param Trigger is the new trigger type for the IRQ source.
* Each bit pair describes the configuration for an INT_ID.
* SFI Read Only b10 always
* PPI Read Only depending on how the PPIs are configured.
* b01 Active HIGH level sensitive
* b11 Rising edge sensitive
* SPI LSB is read only.
* b01 Active HIGH level sensitive
* b11 Rising edge sensitive/
*/
void vPortInterruptSetPriorityTriggerType(u32 Int_Id, u8 Priority, u8 Trigger );
/**
* Sets the target CPU for the interrupt of a peripheral
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Cpu_Id is a CPU number for which the interrupt has to be targeted
* @param Int_Id is the IRQ source number to modify
*/
void vPortInterruptMapToCpu( u8 Cpu_Id, u32 Int_Id );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
......
......@@ -343,14 +343,17 @@ XScuGic_Config *pxGICConfig;
/* Enable interrupts in the ARM. */
Xil_ExceptionEnable();
if( xStatus == XST_SUCCESS )
{
xStatus = pdPASS;
}
else
{
xStatus = pdFAIL;
}
/* Test GIC for operational state */
xStatus |= XScuGic_SelfTest( &xInterruptController );
if( xStatus == XST_SUCCESS )
{
xStatus = pdPASS;
}
else
{
xStatus = pdFAIL;
}
configASSERT( xStatus == pdPASS );
return xStatus;
......@@ -387,6 +390,36 @@ int32_t lReturn;
}
/*-----------------------------------------------------------*/
void vPortInterruptSetPriorityTriggerType(u32 Int_Id, u8 Priority, u8 Trigger )
{
int32_t lReturn;
/* An API function is provided to set the priority of an interrupt in the interrupt
controller. */
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
{
XScuGic_SetPriorityTriggerType( &xInterruptController, Int_Id, Priority, Trigger );
}
configASSERT( lReturn );
}
/*-----------------------------------------------------------*/
void vPortInterruptMapToCpu( u8 Cpu_Id, u32 Int_Id )
{
int32_t lReturn;
/* An API function is provided to map an interrupt in the interrupt
controller to a specific CPU. */
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
{
XScuGic_InterruptMaptoCpu( &xInterruptController, Cpu_Id, Int_Id);
}
configASSERT( lReturn );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
uint32_t ulAPSR;
......
......@@ -66,7 +66,6 @@ XInterval usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
uint32_t timer_offset;
XScuGic_Config *pxInterruptControllerConfig;
timer_offset = 3 * uxHalGetCpuId();
......@@ -95,19 +94,19 @@ XScuGic_Config *pxInterruptControllerConfig;
XTtcPs_SetPrescaler(&xPortTimerTickTtcInstance, ucPrescale );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, configTIMER_INTERRUPT_ID + timer_offset, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
vPortInterruptSetPriorityTriggerType(configTIMER_INTERRUPT_ID + timer_offset,
portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive);
/* This interrupt should be exclusively mapped to this core. */
XScuGic_InterruptMaptoCpu( &xInterruptController, uxHalGetCpuId(), configTIMER_INTERRUPT_ID + timer_offset );
vPortInterruptMapToCpu( uxHalGetCpuId(), configTIMER_INTERRUPT_ID + timer_offset );
/* Connect to the interrupt controller. */
XScuGic_Connect( &xInterruptController,
configTIMER_INTERRUPT_ID + timer_offset,
( Xil_InterruptHandler ) FreeRTOS_Tick_Handler,
( void * ) &xPortTimerTickTtcInstance );
xPortInstallInterruptHandler( configTIMER_INTERRUPT_ID + timer_offset,
( XInterruptHandler ) FreeRTOS_Tick_Handler,
( void * ) &xPortTimerTickTtcInstance );
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, configTIMER_INTERRUPT_ID + timer_offset );
vPortEnableInterrupt( configTIMER_INTERRUPT_ID + timer_offset );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts(&xPortTimerTickTtcInstance, XTTCPS_IXR_INTERVAL_MASK );
......
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