Commit 67b191b6 authored by Oliver Horst's avatar Oliver Horst
Browse files

[chg] Restructured memguard and perfmon code

- Splitted the code into an  architecture specific and a generic part
- Changed naming and formatting to follow the FreeRTOS code style guides
- Implemented a uxHalGetCpuId() method to "universally" provide the information about the core the software is runnign on
parent 808ae201
......@@ -9,3 +9,5 @@ target_sources(
"${CMAKE_CURRENT_LIST_DIR}/portZynqUltrascale.c"
"${CMAKE_CURRENT_LIST_DIR}/port_asm_vectors.S"
)
add_subdirectory(hal)
# SPDX-License-Identifier: MIT
cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
target_sources(
freertos
#
PRIVATE
"${CMAKE_CURRENT_LIST_DIR}/cpu.c"
)
#include "freertos/FreeRTOS.h"
#include "freertos/hal/cpu.h"
#include "xil/xpseudo_asm.h"
/* Multiprocessor Affinity Register - used to retrieve the CPU ID */
#define MPIDR_EL1 "MPIDR_EL1"
/* Mask used for extracting the CPU_ID from the MPIDR_EL1 register */
#define ARM_CA53_CPU_ID_MASK ( (UBaseType_t)( 0xFFu ) )
UBaseType_t uxHalGetCpuId()
{
UBaseType_t uxCpuId;
uxCpuId = mfcp( MPIDR_EL1 );
uxCpuId = uxCpuId & ARM_CA53_CPU_ID_MASK;
return uxCpuId;
}
......@@ -30,7 +30,7 @@
/* FreeRTOS includes. */
#include "freertos/FreeRTOS.h"
#include "freertos/core/task.h"
#include "freertos/arch/arm_ca53/cpuid.h"
#include "freertos/hal/cpu.h"
/* Xilinx includes. */
#include "xil/drivers/xttcps.h"
......@@ -68,9 +68,9 @@ const uint8_t ucLevelSensitive = 1;
uint32_t timer_offset;
XScuGic_Config *pxInterruptControllerConfig;
timer_offset = 3 * get_cpu_id();
timer_offset = 3 * uxHalGetCpuId();
XScuGic_SetCpuID(get_cpu_id());
XScuGic_SetCpuID( uxHalGetCpuId() );
/* Initialize the interrupt controller driver. */
pxInterruptControllerConfig = XScuGic_LookupConfig( configINTERRUPT_CONTROLLER_DEVICE_ID );
......@@ -79,13 +79,13 @@ XScuGic_Config *pxInterruptControllerConfig;
pxInterruptControllerConfig->CpuBaseAddress );
/* By default XScuGic maps all SPI interrupts to the local core so unmap them again. */
XScuGic_UnmapAllInterruptsFromCpu( &xInterruptController, get_cpu_id() );
XScuGic_UnmapAllInterruptsFromCpu( &xInterruptController, uxHalGetCpuId() );
/* Connect the interrupt controller interrupt handler to the hardware
interrupt handling logic in the ARM processor. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_IRQ_INT,
( Xil_ExceptionHandler ) XScuGic_InterruptHandler,
&xInterruptController);
( Xil_ExceptionHandler )XScuGic_InterruptHandler,
&xInterruptController);
/* Enable interrupts in the ARM. */
Xil_ExceptionEnable();
......@@ -118,7 +118,7 @@ XScuGic_Config *pxInterruptControllerConfig;
XScuGic_SetPriorityTriggerType( &xInterruptController, configTIMER_INTERRUPT_ID + timer_offset, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* This interrupt should be exclusively mapped to this core. */
XScuGic_InterruptMaptoCpu( &xInterruptController, get_cpu_id(), configTIMER_INTERRUPT_ID + timer_offset );
XScuGic_InterruptMaptoCpu( &xInterruptController, uxHalGetCpuId(), configTIMER_INTERRUPT_ID + timer_offset );
/* Connect to the interrupt controller. */
XScuGic_Connect( &xInterruptController,
......
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