Commit 808ae201 authored by Johannes Wiesboeck's avatar Johannes Wiesboeck Committed by Oliver Horst
Browse files

[add] Added timer initialization for amp support.

Tick interrupt initialization was adapted to to calculate a Hardware
Timer based on the current core.
parent 48c2262c
......@@ -30,6 +30,7 @@
/* FreeRTOS includes. */
#include "freertos/FreeRTOS.h"
#include "freertos/core/task.h"
#include "freertos/arch/arm_ca53/cpuid.h"
/* Xilinx includes. */
#include "xil/drivers/xttcps.h"
......@@ -64,14 +65,22 @@ XTtcPs_Config *pxTimerConfiguration;
XInterval usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
uint32_t timer_offset;
XScuGic_Config *pxInterruptControllerConfig;
timer_offset = 3 * get_cpu_id();
XScuGic_SetCpuID(get_cpu_id());
/* Initialize the interrupt controller driver. */
pxInterruptControllerConfig = XScuGic_LookupConfig( configINTERRUPT_CONTROLLER_DEVICE_ID );
XScuGic_CfgInitialize( &xInterruptController,
pxInterruptControllerConfig,
pxInterruptControllerConfig->CpuBaseAddress );
/* By default XScuGic maps all SPI interrupts to the local core so unmap them again. */
XScuGic_UnmapAllInterruptsFromCpu( &xInterruptController, get_cpu_id() );
/* Connect the interrupt controller interrupt handler to the hardware
interrupt handling logic in the ARM processor. */
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_IRQ_INT,
......@@ -81,7 +90,7 @@ XScuGic_Config *pxInterruptControllerConfig;
/* Enable interrupts in the ARM. */
Xil_ExceptionEnable();
pxTimerConfiguration = XTtcPs_LookupConfig( configTIMER_ID );
pxTimerConfiguration = XTtcPs_LookupConfig( configTIMER_ID + timer_offset );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
......@@ -106,16 +115,19 @@ XScuGic_Config *pxInterruptControllerConfig;
XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, configTIMER_INTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
XScuGic_SetPriorityTriggerType( &xInterruptController, configTIMER_INTERRUPT_ID + timer_offset, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* This interrupt should be exclusively mapped to this core. */
XScuGic_InterruptMaptoCpu( &xInterruptController, get_cpu_id(), configTIMER_INTERRUPT_ID + timer_offset );
/* Connect to the interrupt controller. */
XScuGic_Connect( &xInterruptController,
configTIMER_INTERRUPT_ID,
configTIMER_INTERRUPT_ID + timer_offset,
( Xil_InterruptHandler ) FreeRTOS_Tick_Handler,
( void * ) &xTimerInstance );
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, configTIMER_INTERRUPT_ID );
XScuGic_Enable( &xInterruptController, configTIMER_INTERRUPT_ID + timer_offset );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment