Commit 9a7ba84a authored by Ulrich Huber's avatar Ulrich Huber Committed by Oliver Horst
Browse files

[chg] Enable extended buffer descriptors in EmacPs driver to gain access to timestamps

parent ac61fbf6
......@@ -433,6 +433,10 @@ extern "C" {
#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_EXTENDED_DESC_ENABLE_OPTION 0x00010000U
/**< Enable the extended buffer descriptors
* This option defaults to disabled (clear) */
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
......@@ -442,7 +446,8 @@ extern "C" {
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_EXTENDED_DESC_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
......
......@@ -91,11 +91,11 @@ extern "C" {
#ifdef __aarch64__
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#define XEMACPS_BD_NUM_WORDS 4U
#define XEMACPS_BD_NUM_WORDS 6U
#else
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#define XEMACPS_BD_NUM_WORDS 2U
#define XEMACPS_BD_NUM_WORDS 4U
#endif
/**
......@@ -400,11 +400,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetRxWrap(BdPtr) \
#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
......@@ -435,11 +435,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetTxWrap(BdPtr) \
#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
......@@ -772,6 +772,88 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Retrieve the BD's Packet timestamp nanoseconds part.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nanoseconds of timestamp
*
* @note
* C-style signature:
* u32 XEmacPs_GetRxNanoseconds(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdGetRxNanoseconds(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_TS_MASK) != 0U ? \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_TIME_OFFSET) & XEMACPS_RXBUF_NSEC_MASK) \
: 0U )
/*****************************************************************************/
/**
* Retrieve the BD's Packet timestamp nanoseconds part.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nanoseconds of timestamp
*
* @note
* C-style signature:
* u32 XEmacPs_GetRxNanoseconds(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdGetTxNanoseconds(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_TS_MASK) != 0U ? \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_TIME_OFFSET) & XEMACPS_TXBUF_NSEC_MASK) \
: 0U )
/*****************************************************************************/
/**
* Retrieve the BD's Packet timestamp seconds part.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nanoseconds of timestamp
*
* @note
* C-style signature:
* u8 XEmacPs_GetRxNanoseconds(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdGetRxSeconds(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_TS_MASK) != 0U ? \
(((XEmacPs_BdRead((BdPtr), XEMACPS_BD_TIME_OFFSET) & \
XEMACPS_RXBUF_SEC_L_MASK) >> 30U) | \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_TIME_OFFSET + 1) & \
XEMACPS_RXBUF_SEC_H_MASK) << 2U)) \
: 0U )
/*****************************************************************************/
/**
* Retrieve the BD's Packet timestamp seconds part.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nanoseconds of timestamp
*
* @note
* C-style signature:
* u8 XEmacPs_GetRxNanoseconds(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdGetTxSeconds(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_TS_MASK) != 0U ? \
(((XEmacPs_BdRead((BdPtr), XEMACPS_BD_TIME_OFFSET) & \
XEMACPS_TXBUF_SEC_L_MASK) >> 30U) | \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_TIME_OFFSET + 1) & \
XEMACPS_TXBUF_SEC_H_MASK) << 2U)) \
: 0U )
/************************** Function Prototypes ******************************/
......
......@@ -540,7 +540,11 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
#if defined(__aarch64__) || defined(__arch64__)
#define XEMACPS_BD_TIME_OFFSET 0x0000000CU /**< word 3/time of BDs */
#else
#define XEMACPS_BD_TIME_OFFSET 0x00000008U /**< word 2/time of BDs */
#endif
/*
* @}
*/
......@@ -563,6 +567,13 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
#define XEMACPS_TXBUF_TS_MASK 0x00800000U /**< Timestamp bit */
#define XEMACPS_TXBUF_NSEC_MASK 0x3FFFFFFFU /**< Mask for nanoseconds */
#define XEMACPS_TXBUF_SEC_L_MASK 0xC0000000U /**< Mask for lower two bits
of seconds */
#define XEMACPS_TXBUF_SEC_H_MASK 0x00000004U /**< Mask for the higher bits
of seconds */
/*
* @}
*/
......@@ -595,9 +606,16 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
#define XEMACPS_RXBUF_TS_MASK 0x00000003U /**< Timestamp bit */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFBU /**< Mask for address */
#define XEMACPS_RXBUF_NSEC_MASK 0x3FFFFFFFU /**< Mask for nanoseconds */
#define XEMACPS_RXBUF_SEC_L_MASK 0xC0000000U /**< Mask for lower two bits
of seconds */
#define XEMACPS_RXBUF_SEC_H_MASK 0x00000004U /**< Mask for the higher bits
of seconds */
/*
* @}
*/
......
......@@ -157,9 +157,6 @@
/************************** Function Prototypes ******************************/
static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
/************************** Variable Definitions *****************************/
/*****************************************************************************/
......@@ -1019,58 +1016,6 @@ LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
return (LONG)(XST_SUCCESS);
}
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
{
u32 DataValueRx;
u32 *TempPtr;
BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
TempPtr = (u32 *)BdPtr;
if(TempPtr != NULL) {
DataValueRx = *TempPtr;
DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
*TempPtr = DataValueRx;
}
}
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
{
u32 DataValueTx;
u32 *TempPtr;
BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
TempPtr = (u32 *)BdPtr;
if(TempPtr != NULL) {
DataValueTx = *TempPtr;
DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
*TempPtr = DataValueTx;
}
}
/*****************************************************************************/
/**
* Reset BD ring head and tail pointers.
......
......@@ -463,135 +463,145 @@ LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
Status = (LONG)(XST_DEVICE_IS_STARTED);
} else {
/* Many of these options will change the NET_CONFIG registers.
* To reduce the amount of IO to the device, group these options here
* and change them all at once.
*/
/* Grab current register contents */
RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
RegNewNetCfg = RegNetCfg;
/*
* It is configured to max 1536.
*/
if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
}
/* Turn on VLAN packet only, only VLAN tagged will be accepted */
if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
}
/* Turn on FCS stripping on receive packets */
if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
}
/* Turn on length/type field checking on receive packets */
if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
}
/* Turn on flow control */
if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
}
/* Turn on promiscuous frame filtering (all frames are received) */
if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
}
/* Allow broadcast address reception */
if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
}
/* Allow multicast address filtering */
if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
}
/* enable RX checksum offload */
if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
}
/* Enable jumbo frames */
if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
(InstancePtr->Version > 2)) {
RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32)(XEMACPS_DMACR_RXBUF_MASK));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
XEMACPS_HDR_VLAN_SIZE;
InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
}
if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
(InstancePtr->Version > 2)) {
RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
XEMACPS_NWCFG_PCSSEL_MASK);
}
/* Officially change the NET_CONFIG registers if it needs to be
* modified.
*/
if (RegNetCfg != RegNewNetCfg) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
}
/* Enable TX checksum offload */
if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
}
/* Enable transmitter */
if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_TXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
}
/* Enable receiver */
if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_RXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
}
/* The remaining options not handled here are managed elsewhere in the
* driver. No register modifications are needed at this time. Reflecting
* the option in InstancePtr->Options is good enough for now.
*/
/* Set options word to its new value */
InstancePtr->Options |= Options;
/* Many of these options will change the NET_CONFIG registers.
* To reduce the amount of IO to the device, group these options here
* and change them all at once.
*/
/* Grab current register contents */
RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
RegNewNetCfg = RegNetCfg;
/*
* It is configured to max 1536.
*/
if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
}
/* Turn on VLAN packet only, only VLAN tagged will be accepted */
if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
}
/* Turn on FCS stripping on receive packets */
if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
}
/* Turn on length/type field checking on receive packets */
if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
}
/* Turn on flow control */
if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
}
/* Turn on promiscuous frame filtering (all frames are received) */
if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
}
/* Allow broadcast address reception */
if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
RegNewNetCfg &= (u32) (~XEMACPS_NWCFG_BCASTDI_MASK);
}
/* Allow multicast address filtering */
if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
}
/* enable RX checksum offload */
if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
}
/* Enable jumbo frames */
if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
(InstancePtr->Version > 2)) {
RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
Reg |= (((((u32) XEMACPS_RX_BUF_SIZE_JUMBO / (u32) XEMACPS_RX_BUF_UNIT) +
(((((u32) XEMACPS_RX_BUF_SIZE_JUMBO %
(u32) XEMACPS_RX_BUF_UNIT)) != (u32) 0) ? 1U : 0U)) <<
(u32) (XEMACPS_DMACR_RXBUF_SHIFT)) &
(u32) (XEMACPS_DMACR_RXBUF_MASK));
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
XEMACPS_HDR_VLAN_SIZE;
InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
}
if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
(InstancePtr->Version > 2)) {
RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
XEMACPS_NWCFG_PCSSEL_MASK);
}
/* Officially change the NET_CONFIG registers if it needs to be
* modified.
*/
if (RegNetCfg != RegNewNetCfg) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
}
/* Enable TX checksum offload */
if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
}
/* Enable transmitter */
if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_TXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
}
/* Enable receiver */
if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET);
Reg |= XEMACPS_NWCTRL_RXEN_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET, Reg);
}
/* Enable extended RX and TX descriptors */
if ((Options & XEMACPS_EXTENDED_DESC_ENABLE_OPTION) != 0x00000000U) {
Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET);
Reg |= XEMACPS_DMACR_TXEXTEND_MASK;
Reg |= XEMACPS_DMACR_RXEXTEND_MASK;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_DMACR_OFFSET, Reg);
}
/* The remaining options not handled here are managed elsewhere in the
* driver. No register modifications are needed at this time. Reflecting
* the option in InstancePtr->Options is good enough for now.
*/
/* Set options word to its new value */
InstancePtr->Options |= Options;
Status = (LONG)(XST_SUCCESS);
}
......
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