[merge] Integrated updates from 'next' branch

- Integrated AMP, memguard, and syscall configuration options
- Updated generated HW description files to XSDK 2019.1
- Updated lwIP config to lwIP 2.x.x
- Fixed heap sizes and heap allocations

CMakeLists.txt

-string(TOLOWER "${PLATFORM}/${TOKI_CONFIG}" CONFIG_DIR)
-add_subdirectory( ${CONFIG_DIR} )
+cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
+
+add_subdirectory( "${TOKI_MACHINE}/${TOKI_OS}/${TOKI_CONFIG}" )

zcu102-zynqmp/baremetal/baseline/master/CMakeLists.txt

+add_subdirectory(ldscript)
+add_subdirectory(libxil)
+add_subdirectory(libxilpm)
+add_subdirectory(sfmt)
+add_subdirectory(toki-extra)

zcu102-zynqmp/baremetal/baseline/master/ldscript/zcu102-zynqmp.ld

+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version:                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2016 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A53 Linker Script                          */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x100000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x08000000;
+
+_TEXT_POOL_SIZE = DEFINED(_TEXT_POOL_SIZE) ? _TEXT_POOL_SIZE : 0x1000000;
+_HEAP_POOL_SIZE = DEFINED(_HEAP_POOL_SIZE) ? _HEAP_POOL_SIZE : 0x2000000;
+
+_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
+_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
+_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
+
+_TOTAL_RAM_SIZE_PER_CORE = DEFINED(_TOTAL_RAM_SIZE_PER_CORE) ? _TOTAL_RAM_SIZE_PER_CORE : 0x20000000;
+
+_AMP_START_ADDRESS = _TOTAL_RAM_SIZE_PER_CORE * _AMP_USE_CORE;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   THIS_CORE : ORIGIN = _AMP_START_ADDRESS, LENGTH = _TOTAL_RAM_SIZE_PER_CORE
+   psu_ddr_0_MEM_0 : ORIGIN = 0x000000000, LENGTH = _TOTAL_RAM_SIZE_PER_CORE
+   psu_ddr_0_MEM_1 : ORIGIN = 0x020000000, LENGTH = _TOTAL_RAM_SIZE_PER_CORE
+   psu_ddr_1_MEM_0 : ORIGIN = 0x040000000, LENGTH = _TOTAL_RAM_SIZE_PER_CORE
+   psu_ddr_1_MEM_1 : ORIGIN = 0x060000000, LENGTH = _TOTAL_RAM_SIZE_PER_CORE
+   psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
+   psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.core_1_bin : {
+   BYTE(0x01)
+   . += 0xfff;
+} > psu_ddr_0_MEM_1 =0x01
+
+.core_2_bin : {
+   BYTE(0x02)
+   . += 0xfff;*/
+} > psu_ddr_1_MEM_0 =0x01
+
+.core_3_bin : {
+   BYTE(0x03)
+   . += 0xfff;
+} > psu_ddr_1_MEM_1 =0x01
+
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > THIS_CORE
+
+.init (ALIGN(64)) : {
+   KEEP (*(.init))
+} > THIS_CORE
+
+.fini (ALIGN(64)) : {
+   KEEP (*(.fini))
+} > THIS_CORE
+
+.interp : {
+   KEEP (*(.interp))
+} > THIS_CORE
+
+.note-ABI-tag : {
+   KEEP (*(.note-ABI-tag))
+} > THIS_CORE
+
+.rodata : {
+   . = ALIGN(64);
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > THIS_CORE
+
+.rodata1 : {
+   . = ALIGN(64);
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > THIS_CORE
+
+.sdata2 : {
+   . = ALIGN(64);
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > THIS_CORE
+
+.sbss2 : {
+   . = ALIGN(64);
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > THIS_CORE
+
+.data : {
+   . = ALIGN(64);
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > THIS_CORE
+
+.data1 : {
+   . = ALIGN(64);
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > THIS_CORE
+
+.got : {
+   *(.got)
+} > THIS_CORE
+
+.got1 : {
+   *(.got1)
+} > THIS_CORE
+
+.got2 : {
+   *(.got2)
+} > THIS_CORE
+
+.ctors : {
+   . = ALIGN(64);
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > THIS_CORE
+
+.dtors : {
+   . = ALIGN(64);
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > THIS_CORE
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > THIS_CORE
+
+.eh_frame : {
+   *(.eh_frame)
+} > THIS_CORE
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > THIS_CORE
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > THIS_CORE
+
+.mmu_tbl0 (ALIGN(4096)) : {
+   __mmu_tbl0_start = .;
+   *(.mmu_tbl0)
+   __mmu_tbl0_end = .;
+} > THIS_CORE
+
+.mmu_tbl1 (ALIGN(4096)) : {
+   __mmu_tbl1_start = .;
+   *(.mmu_tbl1)
+   __mmu_tbl1_end = .;
+} > THIS_CORE
+
+.mmu_tbl2 (ALIGN(4096)) : {
+   __mmu_tbl2_start = .;
+   *(.mmu_tbl2)
+   __mmu_tbl2_end = .;
+} > THIS_CORE
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > THIS_CORE
+
+.preinit_array : {
+   . = ALIGN(64);
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > THIS_CORE
+
+.init_array : {
+   . = ALIGN(64);
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > THIS_CORE
+
+.fini_array : {
+   . = ALIGN(64);
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > THIS_CORE
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > THIS_CORE
+
+.sdata : {
+   . = ALIGN(64);
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > THIS_CORE
+
+.sbss (NOLOAD) : {
+   . = ALIGN(64);
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   . = ALIGN(64);
+   __sbss_end = .;
+} > THIS_CORE
+
+.tdata : {
+   . = ALIGN(64);
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > THIS_CORE
+
+.tbss : {
+   . = ALIGN(64);
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > THIS_CORE
+
+.bss (NOLOAD) : {
+   . = ALIGN(64);
+   __bss_start__ = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   . = ALIGN(64);
+   __bss_end__ = .;
+} > THIS_CORE
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(64);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > THIS_CORE
+
+.text_pool (NOLOAD) : {
+   . = ALIGN(0x10000);
+   TextPoolBase = .;
+   . += _TEXT_POOL_SIZE;
+   TextPoolLimit = .;
+} > THIS_CORE
+
+.heap_pool (NOLOAD) : {
+   . = ALIGN(0x10000);
+   HeapPoolBase = .;
+   . += _HEAP_POOL_SIZE;
+   HeapPoolLimit = .;
+} > THIS_CORE
+
+.stack (NOLOAD) : {
+   . = ALIGN(64);
+   _el3_stack_end = .;
+   . += _STACK_SIZE;
+   __el3_stack = .;
+   _el2_stack_end = .;
+   . += _EL2_STACK_SIZE;
+   . = ALIGN(64);
+   __el2_stack = .;
+   _el1_stack_end = .;
+   . += _EL1_STACK_SIZE;
+   . = ALIGN(64);
+   __el1_stack = .;
+   _el0_stack_end = .;
+   . += _EL0_STACK_SIZE;
+   . = ALIGN(64);
+   __el0_stack = .;
+} > THIS_CORE
+
+_end = .;
+
+.ocm_ram :
+{
+   __ocm_ram_start = .;
+   XCpuBarrierMask1 = .;
+   QUAD(__AMP_CORE_MASK)
+   XCpuBarrierMask2 = .;
+   QUAD(0)
+   KEEP (*(.ocm_ram))
+} > psu_ocm_ram_0_MEM_0
+}

zcu102-zynqmp/baremetal/baseline/master/libxil/CMakeLists.txt

+cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
+
+option(ENABLE_INSTALL "Enable target installation possibility" ON)
+option(WITH_HEADERS "Enable build of separate header library" ON)
+
+
+project(
+    xil-config
+        #
+        VERSION     0.1
+        LANGUAGES   C ASM
+)
+
+find_package(
+    xil-headers 7.0
+    REQUIRED
+)
+
+find_package(
+    toki-libc-repl-headers 0.1
+    REQUIRED
+)
+
+
+add_library(
+    xil-config
+        #
+        STATIC
+            ""
+)
+
+target_link_libraries(
+    xil-config
+        #
+        PUBLIC      xil-headers
+        PRIVATE     toki-libc-repl-headers
+)
+
+
+add_subdirectory(src)
+add_subdirectory(src-gen)
+
+if (WITH_HEADERS)
+    add_subdirectory(include)
+endif()
+
+
+if (ENABLE_INSTALL)
+    # Configure and install the following files:
+    #   - ${PROJECT_NAME}-config.cmake,
+    #   - ${PROJECT_NAME}-config-version.cmake,
+
+    include(CMakePackageConfigHelpers)
+
+    set(ConfigPackageLocation lib/cmake/${PROJECT_NAME}-${PROJECT_VERSION})
+
+    # ${PROJECT_NAME}-config.cmake
+    configure_package_config_file(
+        ${PROJECT_NAME}-config.cmake.in
+        ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config.cmake
+        INSTALL_DESTINATION ${ConfigPackageLocation}
+    )
+
+    # ${PROJECT_NAME}-config-config-version.cmake
+    write_basic_package_version_file(
+        ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config-version.cmake
+        COMPATIBILITY SameMajorVersion
+    )
+
+    # Install exported CMake target files
+    install(
+        TARGETS                     ${PROJECT_NAME}
+        EXPORT                      ${PROJECT_NAME}-targets
+        ARCHIVE DESTINATION         lib
+    )
+
+    install(
+        EXPORT ${PROJECT_NAME}-targets
+        DESTINATION ${ConfigPackageLocation}
+        EXPORT_LINK_INTERFACE_LIBRARIES
+    )
+
+    # Install package/module configuration files
+    install(
+        FILES
+        ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config.cmake
+        ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config-version.cmake
+        DESTINATION ${ConfigPackageLocation}
+    )
+
+
+    install(
+        EXPORT ${PROJECT_NAME}-targets
+        DESTINATION ${ConfigPackageLocation}
+        EXPORT_LINK_INTERFACE_LIBRARIES
+    )
+endif()

zcu102-zynqmp/baremetal/baseline/master/libxil/include/CMakeLists.txt

+cmake_minimum_required(VERSION 3.7 FATAL_ERROR)
+
+option(ENABLE_INSTALL "Enable target installation possibility" ON)
+
+
+project(
+    xil-config-headers
+        #
+        VERSION     0.1
+        LANGUAGES   C ASM
+)
+
+
+add_library(
+    xil-config-headers
+        #
+        INTERFACE
+)
+
+target_include_directories(
+    xil-config-headers
+        #
+        INTERFACE       $<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}>
+                        $<INSTALL_INTERFACE:include>
+)
+
+target_compile_definitions(
+    xil-config-headers
+        #
+        INTERFACE       XIL_ARCH=arm_ca53
+)
+
+
+if (ENABLE_INSTALL)
+    # Configure and install the following files:
+    #   - ${PROJECT_NAME}-config.cmake,
+    #   - ${PROJECT_NAME}-config-version.cmake,
+
+    include(CMakePackageConfigHelpers)
+
+    set(ConfigPackageLocation lib/cmake/${PROJECT_NAME}-${PROJECT_VERSION})
+
+    # ${PROJECT_NAME}-config.cmake
+    configure_package_config_file(
+            ${PROJECT_NAME}-config.cmake.in
+            ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config.cmake
+            INSTALL_DESTINATION ${ConfigPackageLocation}
+    )
+
+    # ${PROJECT_NAME}-config-config-version.cmake
+    write_basic_package_version_file(
+            ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config-version.cmake
+            COMPATIBILITY SameMajorVersion
+    )
+
+    # Install exported CMake target files
+    install(
+            TARGETS                     ${PROJECT_NAME}
+            EXPORT                      ${PROJECT_NAME}-targets
+            ARCHIVE DESTINATION         lib
+    )
+
+    install(
+            EXPORT ${PROJECT_NAME}-targets
+            DESTINATION ${ConfigPackageLocation}
+            EXPORT_LINK_INTERFACE_LIBRARIES
+    )
+
+    # Install package/module configuration files
+    install(
+            FILES
+            ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config.cmake
+            ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}-config-version.cmake
+            DESTINATION ${ConfigPackageLocation}
+    )
+
+    # If desired install all header files of the current project
+    get_target_property(PROJECT_INCLUDE_DIRECTORIES ${PROJECT_NAME} INTERFACE_INCLUDE_DIRECTORIES)
+
+    foreach(DIR ${PROJECT_INCLUDE_DIRECTORIES})
+
+        string(REGEX MATCH "^.<BUILD_INTERFACE:(.*)>$" EXTRACTED_DIR ${DIR})
+
+        if (CMAKE_MATCH_1)
+            set(EXTRACTED_DIR "${CMAKE_MATCH_1}")
+
+            file(
+                    GLOB_RECURSE
+                    #
+                    HEADER_FILES
+                    #
+                    FOLLOW_SYMLINKS
+                    LIST_DIRECTORIES    FALSE
+                    RELATIVE            "${EXTRACTED_DIR}"
+                    #
+                    "${EXTRACTED_DIR}/*.h"
+                    "${EXTRACTED_DIR}/*.hpp"
+            )
+
+            foreach(FILE ${HEADER_FILES})
+                get_filename_component(INSTALL_PATH ${FILE} DIRECTORY)
+
+                install(
+                        FILES           ${EXTRACTED_DIR}/${FILE}
+                        DESTINATION     include/${INSTALL_PATH}
+                )
+            endforeach()
+        endif()
+    endforeach()
+endif()

zcu102-zynqmp/baremetal/baseline/master/libxil/include/xil/bspconfig.h

+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions: