Commit dcf2b674 authored by Ulrich Huber's avatar Ulrich Huber
Browse files

[chg] Update generated source files to Vitis 2020.2

parent 3b4ecbec
......@@ -2,35 +2,11 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* Version: 2020.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
* Description: Configurations for Standalone BSP
......
......@@ -365,6 +365,26 @@
#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF
/******************************************************************/
#define XPAR_PSU_DP_LANE_COUNT 1
/* Definitions for driver DPPSU */
#define XPAR_XDPPSU_NUM_INSTANCES 1
/* Definitions for peripheral PSU_DP */
#define XPAR_PSU_DP_DEVICE_ID 0
#define XPAR_PSU_DP_BASEADDR 0xFD4A0000
#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF
/******************************************************************/
/* Canonical definitions for peripheral PSU_DP */
#define XPAR_XDPPSU_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID
#define XPAR_XDPPSU_0_BASEADDR 0xFD4A0000
#define XPAR_XDPPSU_0_HIGHADDR 0xFD4AFFFF
/******************************************************************/
/* Definitions for driver EMACPS */
......@@ -388,6 +408,7 @@
#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_ETHERNET_3_REF_CLK GEM3_REF
/* Canonical definitions for peripheral PSU_ETHERNET_3 */
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
......@@ -460,6 +481,11 @@
#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF
/* Definitions for peripheral PSU_CSU_0 */
#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000
#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF
/* Definitions for peripheral PSU_CTRL_IPI */
#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000
#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF
......@@ -783,6 +809,10 @@
/******************************************************************/
/* Definition for input Clock */
#define XPAR_PSU_I2C_0_REF_CLK I2C0_REF
/* Definition for input Clock */
#define XPAR_PSU_I2C_1_REF_CLK I2C1_REF
#define XPAR_XIPIPSU_NUM_INSTANCES 1U
/* Parameter definitions for peripheral psu_ipi_0 */
......@@ -956,6 +986,7 @@
/******************************************************************/
#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_QSPI_0_REF_CLK QSPI_REF
/* Canonical definitions for peripheral PSU_QSPI_0 */
#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000
......@@ -1021,7 +1052,10 @@
/******************************************************************/
/* Definitions for Fabric interrupts connected to psu_acpu_gic */
#define XPAR_FABRIC_INTGEN_TRIGGER_INTR 121U
#define XPAR_FABRIC_INTGEN_0_TRIGGER_0_INTR 121U
#define XPAR_FABRIC_INTGEN_0_TRIGGER_1_INTR 122U
#define XPAR_FABRIC_INTGEN_0_TRIGGER_2_INTR 123U
#define XPAR_FABRIC_INTGEN_0_TRIGGER_3_INTR 124U
/******************************************************************/
......@@ -1068,6 +1102,7 @@
/******************************************************************/
#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0
#define XPAR_PSU_SD_1_REF_CLK SDIO1_REF
/* Canonical definitions for peripheral PSU_SD_1 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xFF170000
......@@ -1237,28 +1272,25 @@
/******************************************************************/
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_XUARTLITE_NUM_INSTANCES 1U
/* Definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_AXI_UARTLITE_0_BASEADDR 0xB0000000
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0xB0000FFF
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0
#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8
/******************************************************************/
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0U
#define XPAR_AXI_UARTLITE_0_BASEADDR 0xB0000000U
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0xB0000FFFU
#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600U
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0U
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0U
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8U
/* Canonical definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0xB0000000
#define XPAR_UARTLITE_0_HIGHADDR 0xB0000FFF
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_DEVICE_ID 0U
#define XPAR_UARTLITE_0_BASEADDR 0xB0000000U
#define XPAR_UARTLITE_0_HIGHADDR 0xB0000FFFU
#define XPAR_UARTLITE_0_BAUDRATE 9600U
#define XPAR_UARTLITE_0_USE_PARITY 0U
#define XPAR_UARTLITE_0_ODD_PARITY 0U
#define XPAR_UARTLITE_0_DATA_BITS 8U
/******************************************************************/
......@@ -1301,6 +1333,10 @@
/******************************************************************/
/* Definition for input Clock */
#define XPAR_PSU_UART_0_REF_CLK UART0_REF
/* Definition for input Clock */
#define XPAR_PSU_UART_1_REF_CLK UART1_REF
/* Definitions for driver USBPSU */
#define XPAR_XUSBPSU_NUM_INSTANCES 1
......@@ -1313,6 +1349,7 @@
/******************************************************************/
#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_USB_XHCI_0_REF_CLK USB0_BUS_REF
#define XPAR_PSU_USB_XHCI_0_SUPER_SPEED 1
/* Canonical definitions for peripheral PSU_USB_XHCI_0 */
#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID
......
/******************************************************************************
*
* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
......@@ -166,7 +144,7 @@ extern "C" {
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for backwards compatibilty
* within the hardblock. These have been put for backwards compatibility
*/
......@@ -306,7 +284,7 @@ extern "C" {
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
/* For backwards compatibility */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
......
......@@ -10,16 +10,22 @@ target_sources(
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xcanps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xclockps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xcsudma_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xdpdma_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xdppsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xemacps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xgpio_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xgpiops_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xiicps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xipipsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xpciepsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xqspipsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xresetps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xrtcpsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xscugic_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xsdps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xsysmonpsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xttcps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xuartlite_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xuartps_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xusbpsu_g.c>
$<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}/xwdtps_g.c>
......
......@@ -2,33 +2,13 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1
* Version: 2020.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
*
* Description: Driver configuration
*
*******************************************************************/
......@@ -41,83 +21,83 @@
*/
XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] =
{
{
XPAR_PSU_APM_0_DEVICE_ID,
XPAR_PSU_APM_0_BASEADDR,
XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_0_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_0_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_0_NUM_OF_COUNTERS,
XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_0_ENABLE_EVENT_LOG,
XPAR_PSU_APM_0_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_0_METRIC_COUNT_SCALE,
XPAR_PSU_APM_0_ENABLE_ADVANCED,
XPAR_PSU_APM_0_ENABLE_PROFILE,
XPAR_PSU_APM_0_ENABLE_TRACE,
XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID
},
{
XPAR_PSU_APM_1_DEVICE_ID,
XPAR_PSU_APM_1_BASEADDR,
XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_1_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_1_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_1_NUM_OF_COUNTERS,
XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_1_ENABLE_EVENT_LOG,
XPAR_PSU_APM_1_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_1_METRIC_COUNT_SCALE,
XPAR_PSU_APM_1_ENABLE_ADVANCED,
XPAR_PSU_APM_1_ENABLE_PROFILE,
XPAR_PSU_APM_1_ENABLE_TRACE,
XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID
},
{
XPAR_PSU_APM_2_DEVICE_ID,
XPAR_PSU_APM_2_BASEADDR,
XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_2_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_2_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_2_NUM_OF_COUNTERS,
XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_2_ENABLE_EVENT_LOG,
XPAR_PSU_APM_2_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_2_METRIC_COUNT_SCALE,
XPAR_PSU_APM_2_ENABLE_ADVANCED,
XPAR_PSU_APM_2_ENABLE_PROFILE,
XPAR_PSU_APM_2_ENABLE_TRACE,
XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID
},
{
XPAR_PSU_APM_5_DEVICE_ID,
XPAR_PSU_APM_5_BASEADDR,
XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_5_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_5_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_5_NUM_OF_COUNTERS,
XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_5_ENABLE_EVENT_LOG,
XPAR_PSU_APM_5_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_5_METRIC_COUNT_SCALE,
XPAR_PSU_APM_5_ENABLE_ADVANCED,
XPAR_PSU_APM_5_ENABLE_PROFILE,
XPAR_PSU_APM_5_ENABLE_TRACE,
XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID
}
};
{
{
XPAR_PSU_APM_0_DEVICE_ID,
XPAR_PSU_APM_0_BASEADDR,
XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_0_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_0_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_0_NUM_OF_COUNTERS,
XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_0_ENABLE_EVENT_LOG,
XPAR_PSU_APM_0_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_0_METRIC_COUNT_SCALE,
XPAR_PSU_APM_0_ENABLE_ADVANCED,
XPAR_PSU_APM_0_ENABLE_PROFILE,
XPAR_PSU_APM_0_ENABLE_TRACE,
XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID
},
{
XPAR_PSU_APM_1_DEVICE_ID,
XPAR_PSU_APM_1_BASEADDR,
XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_1_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_1_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_1_NUM_OF_COUNTERS,
XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_1_ENABLE_EVENT_LOG,
XPAR_PSU_APM_1_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_1_METRIC_COUNT_SCALE,
XPAR_PSU_APM_1_ENABLE_ADVANCED,
XPAR_PSU_APM_1_ENABLE_PROFILE,
XPAR_PSU_APM_1_ENABLE_TRACE,
XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID
},
{
XPAR_PSU_APM_2_DEVICE_ID,
XPAR_PSU_APM_2_BASEADDR,
XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_2_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_2_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_2_NUM_OF_COUNTERS,
XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_2_ENABLE_EVENT_LOG,
XPAR_PSU_APM_2_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_2_METRIC_COUNT_SCALE,
XPAR_PSU_APM_2_ENABLE_ADVANCED,
XPAR_PSU_APM_2_ENABLE_PROFILE,
XPAR_PSU_APM_2_ENABLE_TRACE,
XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID
},
{
XPAR_PSU_APM_5_DEVICE_ID,
XPAR_PSU_APM_5_BASEADDR,
XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH,
XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH,
XPAR_PSU_APM_5_ENABLE_EVENT_COUNT,
XPAR_PSU_APM_5_NUM_MONITOR_SLOTS,
XPAR_PSU_APM_5_NUM_OF_COUNTERS,
XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT,
XPAR_PSU_APM_5_ENABLE_EVENT_LOG,
XPAR_PSU_APM_5_FIFO_AXIS_DEPTH,
XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH,
XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH,
XPAR_PSU_APM_5_METRIC_COUNT_SCALE,
XPAR_PSU_APM_5_ENABLE_ADVANCED,
XPAR_PSU_APM_5_ENABLE_PROFILE,
XPAR_PSU_APM_5_ENABLE_TRACE,
XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID
}
};
......@@ -2,33 +2,13 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1
* Version: 2020.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
*
* Description: Driver configuration
*
*******************************************************************/
......@@ -41,11 +21,11 @@
*/
XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] =
{
{
XPAR_PSU_CAN_1_DEVICE_ID,
XPAR_PSU_CAN_1_BASEADDR
}
};
{
{
XPAR_PSU_CAN_1_DEVICE_ID,
XPAR_PSU_CAN_1_BASEADDR
}
};
/******************************************************************************
*
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
* Copyright (C) 2018 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xclockps_g.c
* @addtogroup xclockps_v1_0
* @addtogroup xclockps_v1_3
* @{
*
* This file contains a table that specifies the configuration of the clocking
......@@ -63,10 +41,9 @@
* the system.
*/
XClockPs_Config XClockPs_ConfigTable[XPAR_XCLOCKPS_NUM_INSTANCES] = {
{
(u16)XPAR_XCLOCKPS_DEVICE_ID,
}
{
(u16)XPAR_XCLOCKPS_DEVICE_ID,
}
};
/** @} */
......@@ -2,33 +2,13 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1
* Version: 2020.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.