Commit 798260b2 authored by Oliver Horst's avatar Oliver Horst
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
// Date : Mon Jan 14 18:14:09 2019
// Host : pc0v9npk running 64-bit Ubuntu 18.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ config_mpsoc_ddr4_0_0_stub.v
// Design : config_mpsoc_ddr4_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xczu9eg-ffvb1156-2-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ddr4_v2_2_6,Vivado 2018.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_rst, c0_sys_clk_p, c0_sys_clk_n,
c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n,
c0_ddr4_ck_t, c0_ddr4_ck_c, c0_ddr4_reset_n, c0_ddr4_dm_dbi_n, c0_ddr4_dq, c0_ddr4_dqs_c,
c0_ddr4_dqs_t, c0_init_calib_complete, c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst,
addn_ui_clkout1, dbg_clk, c0_ddr4_aresetn, c0_ddr4_s_axi_awid, c0_ddr4_s_axi_awaddr,
c0_ddr4_s_axi_awlen, c0_ddr4_s_axi_awsize, c0_ddr4_s_axi_awburst, c0_ddr4_s_axi_awlock,
c0_ddr4_s_axi_awcache, c0_ddr4_s_axi_awprot, c0_ddr4_s_axi_awqos,
c0_ddr4_s_axi_awvalid, c0_ddr4_s_axi_awready, c0_ddr4_s_axi_wdata, c0_ddr4_s_axi_wstrb,
c0_ddr4_s_axi_wlast, c0_ddr4_s_axi_wvalid, c0_ddr4_s_axi_wready, c0_ddr4_s_axi_bready,
c0_ddr4_s_axi_bid, c0_ddr4_s_axi_bresp, c0_ddr4_s_axi_bvalid, c0_ddr4_s_axi_arid,
c0_ddr4_s_axi_araddr, c0_ddr4_s_axi_arlen, c0_ddr4_s_axi_arsize, c0_ddr4_s_axi_arburst,
c0_ddr4_s_axi_arlock, c0_ddr4_s_axi_arcache, c0_ddr4_s_axi_arprot, c0_ddr4_s_axi_arqos,
c0_ddr4_s_axi_arvalid, c0_ddr4_s_axi_arready, c0_ddr4_s_axi_rready, c0_ddr4_s_axi_rid,
c0_ddr4_s_axi_rdata, c0_ddr4_s_axi_rresp, c0_ddr4_s_axi_rlast, c0_ddr4_s_axi_rvalid,
dbg_bus)
/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[0:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_dm_dbi_n[1:0],c0_ddr4_dq[15:0],c0_ddr4_dqs_c[1:0],c0_ddr4_dqs_t[1:0],c0_init_calib_complete,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,addn_ui_clkout1,dbg_clk,c0_ddr4_aresetn,c0_ddr4_s_axi_awid[0:0],c0_ddr4_s_axi_awaddr[28:0],c0_ddr4_s_axi_awlen[7:0],c0_ddr4_s_axi_awsize[2:0],c0_ddr4_s_axi_awburst[1:0],c0_ddr4_s_axi_awlock[0:0],c0_ddr4_s_axi_awcache[3:0],c0_ddr4_s_axi_awprot[2:0],c0_ddr4_s_axi_awqos[3:0],c0_ddr4_s_axi_awvalid,c0_ddr4_s_axi_awready,c0_ddr4_s_axi_wdata[127:0],c0_ddr4_s_axi_wstrb[15:0],c0_ddr4_s_axi_wlast,c0_ddr4_s_axi_wvalid,c0_ddr4_s_axi_wready,c0_ddr4_s_axi_bready,c0_ddr4_s_axi_bid[0:0],c0_ddr4_s_axi_bresp[1:0],c0_ddr4_s_axi_bvalid,c0_ddr4_s_axi_arid[0:0],c0_ddr4_s_axi_araddr[28:0],c0_ddr4_s_axi_arlen[7:0],c0_ddr4_s_axi_arsize[2:0],c0_ddr4_s_axi_arburst[1:0],c0_ddr4_s_axi_arlock[0:0],c0_ddr4_s_axi_arcache[3:0],c0_ddr4_s_axi_arprot[2:0],c0_ddr4_s_axi_arqos[3:0],c0_ddr4_s_axi_arvalid,c0_ddr4_s_axi_arready,c0_ddr4_s_axi_rready,c0_ddr4_s_axi_rid[0:0],c0_ddr4_s_axi_rdata[127:0],c0_ddr4_s_axi_rresp[1:0],c0_ddr4_s_axi_rlast,c0_ddr4_s_axi_rvalid,dbg_bus[511:0]" */;
input sys_rst;
input c0_sys_clk_p;
input c0_sys_clk_n;
output c0_ddr4_act_n;
output [16:0]c0_ddr4_adr;
output [1:0]c0_ddr4_ba;
output [0:0]c0_ddr4_bg;
output [0:0]c0_ddr4_cke;
output [0:0]c0_ddr4_odt;
output [0:0]c0_ddr4_cs_n;
output [0:0]c0_ddr4_ck_t;
output [0:0]c0_ddr4_ck_c;
output c0_ddr4_reset_n;
inout [1:0]c0_ddr4_dm_dbi_n;
inout [15:0]c0_ddr4_dq;
inout [1:0]c0_ddr4_dqs_c;
inout [1:0]c0_ddr4_dqs_t;
output c0_init_calib_complete;
output c0_ddr4_ui_clk;
output c0_ddr4_ui_clk_sync_rst;
output addn_ui_clkout1;
output dbg_clk;
input c0_ddr4_aresetn;
input [0:0]c0_ddr4_s_axi_awid;
input [28:0]c0_ddr4_s_axi_awaddr;
input [7:0]c0_ddr4_s_axi_awlen;
input [2:0]c0_ddr4_s_axi_awsize;
input [1:0]c0_ddr4_s_axi_awburst;
input [0:0]c0_ddr4_s_axi_awlock;
input [3:0]c0_ddr4_s_axi_awcache;
input [2:0]c0_ddr4_s_axi_awprot;
input [3:0]c0_ddr4_s_axi_awqos;
input c0_ddr4_s_axi_awvalid;
output c0_ddr4_s_axi_awready;
input [127:0]c0_ddr4_s_axi_wdata;
input [15:0]c0_ddr4_s_axi_wstrb;
input c0_ddr4_s_axi_wlast;
input c0_ddr4_s_axi_wvalid;
output c0_ddr4_s_axi_wready;
input c0_ddr4_s_axi_bready;
output [0:0]c0_ddr4_s_axi_bid;
output [1:0]c0_ddr4_s_axi_bresp;
output c0_ddr4_s_axi_bvalid;
input [0:0]c0_ddr4_s_axi_arid;
input [28:0]c0_ddr4_s_axi_araddr;
input [7:0]c0_ddr4_s_axi_arlen;
input [2:0]c0_ddr4_s_axi_arsize;
input [1:0]c0_ddr4_s_axi_arburst;
input [0:0]c0_ddr4_s_axi_arlock;
input [3:0]c0_ddr4_s_axi_arcache;
input [2:0]c0_ddr4_s_axi_arprot;
input [3:0]c0_ddr4_s_axi_arqos;
input c0_ddr4_s_axi_arvalid;
output c0_ddr4_s_axi_arready;
input c0_ddr4_s_axi_rready;
output [0:0]c0_ddr4_s_axi_rid;
output [127:0]c0_ddr4_s_axi_rdata;
output [1:0]c0_ddr4_s_axi_rresp;
output c0_ddr4_s_axi_rlast;
output c0_ddr4_s_axi_rvalid;
output [511:0]dbg_bus;
endmodule
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
-- Date : Mon Jan 14 18:14:09 2019
-- Host : pc0v9npk running 64-bit Ubuntu 18.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ config_mpsoc_ddr4_0_0_stub.vhdl
-- Design : config_mpsoc_ddr4_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xczu9eg-ffvb1156-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sys_rst : in STD_LOGIC;
c0_sys_clk_p : in STD_LOGIC;
c0_sys_clk_n : in STD_LOGIC;
c0_ddr4_act_n : out STD_LOGIC;
c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_bg : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_reset_n : out STD_LOGIC;
c0_ddr4_dm_dbi_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 1 downto 0 );
c0_init_calib_complete : out STD_LOGIC;
c0_ddr4_ui_clk : out STD_LOGIC;
c0_ddr4_ui_clk_sync_rst : out STD_LOGIC;
addn_ui_clkout1 : out STD_LOGIC;
dbg_clk : out STD_LOGIC;
c0_ddr4_aresetn : in STD_LOGIC;
c0_ddr4_s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_awaddr : in STD_LOGIC_VECTOR ( 28 downto 0 );
c0_ddr4_s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
c0_ddr4_s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_awvalid : in STD_LOGIC;
c0_ddr4_s_axi_awready : out STD_LOGIC;
c0_ddr4_s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
c0_ddr4_s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
c0_ddr4_s_axi_wlast : in STD_LOGIC;
c0_ddr4_s_axi_wvalid : in STD_LOGIC;
c0_ddr4_s_axi_wready : out STD_LOGIC;
c0_ddr4_s_axi_bready : in STD_LOGIC;
c0_ddr4_s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_bvalid : out STD_LOGIC;
c0_ddr4_s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_araddr : in STD_LOGIC_VECTOR ( 28 downto 0 );
c0_ddr4_s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
c0_ddr4_s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_arvalid : in STD_LOGIC;
c0_ddr4_s_axi_arready : out STD_LOGIC;
c0_ddr4_s_axi_rready : in STD_LOGIC;
c0_ddr4_s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
c0_ddr4_s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_rlast : out STD_LOGIC;
c0_ddr4_s_axi_rvalid : out STD_LOGIC;
dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[0:0],c0_ddr4_cke[0:0],c0_ddr4_odt[0:0],c0_ddr4_cs_n[0:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_dm_dbi_n[1:0],c0_ddr4_dq[15:0],c0_ddr4_dqs_c[1:0],c0_ddr4_dqs_t[1:0],c0_init_calib_complete,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,addn_ui_clkout1,dbg_clk,c0_ddr4_aresetn,c0_ddr4_s_axi_awid[0:0],c0_ddr4_s_axi_awaddr[28:0],c0_ddr4_s_axi_awlen[7:0],c0_ddr4_s_axi_awsize[2:0],c0_ddr4_s_axi_awburst[1:0],c0_ddr4_s_axi_awlock[0:0],c0_ddr4_s_axi_awcache[3:0],c0_ddr4_s_axi_awprot[2:0],c0_ddr4_s_axi_awqos[3:0],c0_ddr4_s_axi_awvalid,c0_ddr4_s_axi_awready,c0_ddr4_s_axi_wdata[127:0],c0_ddr4_s_axi_wstrb[15:0],c0_ddr4_s_axi_wlast,c0_ddr4_s_axi_wvalid,c0_ddr4_s_axi_wready,c0_ddr4_s_axi_bready,c0_ddr4_s_axi_bid[0:0],c0_ddr4_s_axi_bresp[1:0],c0_ddr4_s_axi_bvalid,c0_ddr4_s_axi_arid[0:0],c0_ddr4_s_axi_araddr[28:0],c0_ddr4_s_axi_arlen[7:0],c0_ddr4_s_axi_arsize[2:0],c0_ddr4_s_axi_arburst[1:0],c0_ddr4_s_axi_arlock[0:0],c0_ddr4_s_axi_arcache[3:0],c0_ddr4_s_axi_arprot[2:0],c0_ddr4_s_axi_arqos[3:0],c0_ddr4_s_axi_arvalid,c0_ddr4_s_axi_arready,c0_ddr4_s_axi_rready,c0_ddr4_s_axi_rid[0:0],c0_ddr4_s_axi_rdata[127:0],c0_ddr4_s_axi_rresp[1:0],c0_ddr4_s_axi_rlast,c0_ddr4_s_axi_rvalid,dbg_bus[511:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_6,Vivado 2018.3";
begin
end;
NumberHits:3
Timestamp: Mon Jan 14 23:29:35 UTC 2019
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
// Date : Mon Jan 14 18:09:18 2019
// Host : pc0v9npk running 64-bit Ubuntu 18.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ config_mpsoc_auto_pc_0_stub.v
// Design : config_mpsoc_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xczu9eg-ffvb1156-2-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_18_axi_protocol_converter,Vivado 2018.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[39:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[39:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[39:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[39:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [39:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [39:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [39:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [39:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
-- Date : Mon Jan 14 18:09:19 2019
-- Host : pc0v9npk running 64-bit Ubuntu 18.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ config_mpsoc_auto_pc_0_stub.vhdl
-- Design : config_mpsoc_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xczu9eg-ffvb1156-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[39:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[39:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[39:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[39:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_18_axi_protocol_converter,Vivado 2018.3";
begin
end;
NumberHits:3
Timestamp: Mon Jan 14 23:29:38 UTC 2019
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